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@@ -547,6 +547,11 @@ int __init mx6q_clocks_init(void)
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clk_register_clkdev(clk[cko1], "cko1", NULL);
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clk_register_clkdev(clk[arm], NULL, "cpu0");
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+ if (imx6q_revision() != IMX_CHIP_REVISION_1_0) {
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+ clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
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+ clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
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+ }
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+
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/*
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* The gpmi needs 100MHz frequency in the EDO/Sync mode,
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* We can not get the 100MHz from the pll2_pfd0_352m.
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