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@@ -0,0 +1,146 @@
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+/*
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+ * QUICC Engine GPIOs
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+ *
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+ * Copyright (c) MontaVista Software, Inc. 2008.
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+ *
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+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/spinlock.h>
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+#include <linux/io.h>
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+#include <linux/of.h>
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+#include <linux/of_gpio.h>
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+#include <linux/gpio.h>
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+#include <asm/qe.h>
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+
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+struct qe_gpio_chip {
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+ struct of_mm_gpio_chip mm_gc;
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+ spinlock_t lock;
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+
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+ /* shadowed data register to clear/set bits safely */
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+ u32 cpdata;
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+};
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+
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+static inline struct qe_gpio_chip *
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+to_qe_gpio_chip(struct of_mm_gpio_chip *mm_gc)
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+{
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+ return container_of(mm_gc, struct qe_gpio_chip, mm_gc);
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+}
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+
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+static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
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+{
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+ struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
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+ struct qe_pio_regs __iomem *regs = mm_gc->regs;
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+
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+ qe_gc->cpdata = in_be32(®s->cpdata);
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+}
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+
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+static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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+{
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+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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+ struct qe_pio_regs __iomem *regs = mm_gc->regs;
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+ u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
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+
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+ return in_be32(®s->cpdata) & pin_mask;
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+}
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+
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+static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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+{
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+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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+ struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
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+ struct qe_pio_regs __iomem *regs = mm_gc->regs;
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+ unsigned long flags;
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+ u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
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+
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+ spin_lock_irqsave(&qe_gc->lock, flags);
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+
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+ if (val)
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+ qe_gc->cpdata |= pin_mask;
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+ else
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+ qe_gc->cpdata &= ~pin_mask;
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+
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+ out_be32(®s->cpdata, qe_gc->cpdata);
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+
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+ spin_unlock_irqrestore(&qe_gc->lock, flags);
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+}
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+
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+static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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+{
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+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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+ struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&qe_gc->lock, flags);
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+
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+ __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
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+
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+ spin_unlock_irqrestore(&qe_gc->lock, flags);
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+
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+ return 0;
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+}
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+
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+static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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+{
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+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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+ struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&qe_gc->lock, flags);
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+
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+ __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
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+
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+ spin_unlock_irqrestore(&qe_gc->lock, flags);
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+
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+ qe_gpio_set(gc, gpio, val);
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+
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+ return 0;
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+}
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+
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+void __init qe_add_gpiochips(void)
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+{
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+ struct device_node *np;
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+
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+ for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
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+ int ret;
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+ struct qe_gpio_chip *qe_gc;
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+ struct of_mm_gpio_chip *mm_gc;
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+ struct of_gpio_chip *of_gc;
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+ struct gpio_chip *gc;
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+
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+ qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
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+ if (!qe_gc) {
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+ ret = -ENOMEM;
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+ goto err;
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+ }
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+
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+ spin_lock_init(&qe_gc->lock);
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+
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+ mm_gc = &qe_gc->mm_gc;
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+ of_gc = &mm_gc->of_gc;
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+ gc = &of_gc->gc;
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+
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+ mm_gc->save_regs = qe_gpio_save_regs;
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+ of_gc->gpio_cells = 2;
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+ gc->ngpio = QE_PIO_PINS;
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+ gc->direction_input = qe_gpio_dir_in;
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+ gc->direction_output = qe_gpio_dir_out;
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+ gc->get = qe_gpio_get;
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+ gc->set = qe_gpio_set;
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+
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+ ret = of_mm_gpiochip_add(np, mm_gc);
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+ if (ret)
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+ goto err;
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+ continue;
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+err:
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+ pr_err("%s: registration failed with status %d\n",
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+ np->full_name, ret);
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+ kfree(qe_gc);
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+ /* try others anyway */
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+ }
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+}
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