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@@ -5,6 +5,7 @@
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*
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* Copyright (c) 2010 Nokia Corporation
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* Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
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+ * Copyright (c) 2011 Texas Instruments Incorporated
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as published
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@@ -19,28 +20,39 @@
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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-#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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+#include <linux/dmaengine.h>
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+#include <linux/omap-dma.h>
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+#include <linux/pm_runtime.h>
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+#include <linux/of.h>
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+#include <linux/of_device.h>
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+#include <linux/of_address.h>
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#include <linux/io.h>
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#include <linux/crypto.h>
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#include <linux/interrupt.h>
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#include <crypto/scatterwalk.h>
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#include <crypto/aes.h>
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-#include <linux/omap-dma.h>
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+#define DST_MAXBURST 4
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+#define DMA_MIN (DST_MAXBURST * sizeof(u32))
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/* OMAP TRM gives bitfields as start:end, where start is the higher bit
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number. For example 7:0 */
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#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
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#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
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-#define AES_REG_KEY(x) (0x1C - ((x ^ 0x01) * 0x04))
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-#define AES_REG_IV(x) (0x20 + ((x) * 0x04))
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+#define AES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
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+ ((x ^ 0x01) * 0x04))
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+#define AES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
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-#define AES_REG_CTRL 0x30
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-#define AES_REG_CTRL_CTR_WIDTH (1 << 7)
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+#define AES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
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+#define AES_REG_CTRL_CTR_WIDTH_MASK (3 << 7)
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+#define AES_REG_CTRL_CTR_WIDTH_32 (0 << 7)
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+#define AES_REG_CTRL_CTR_WIDTH_64 (1 << 7)
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+#define AES_REG_CTRL_CTR_WIDTH_96 (2 << 7)
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+#define AES_REG_CTRL_CTR_WIDTH_128 (3 << 7)
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#define AES_REG_CTRL_CTR (1 << 6)
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#define AES_REG_CTRL_CBC (1 << 5)
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#define AES_REG_CTRL_KEY_SIZE (3 << 3)
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@@ -48,14 +60,11 @@
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#define AES_REG_CTRL_INPUT_READY (1 << 1)
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#define AES_REG_CTRL_OUTPUT_READY (1 << 0)
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-#define AES_REG_DATA 0x34
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-#define AES_REG_DATA_N(x) (0x34 + ((x) * 0x04))
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+#define AES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
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-#define AES_REG_REV 0x44
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-#define AES_REG_REV_MAJOR 0xF0
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-#define AES_REG_REV_MINOR 0x0F
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+#define AES_REG_REV(dd) ((dd)->pdata->rev_ofs)
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-#define AES_REG_MASK 0x48
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+#define AES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
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#define AES_REG_MASK_SIDLE (1 << 6)
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#define AES_REG_MASK_START (1 << 5)
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#define AES_REG_MASK_DMA_OUT_EN (1 << 3)
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@@ -63,8 +72,7 @@
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#define AES_REG_MASK_SOFTRESET (1 << 1)
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#define AES_REG_AUTOIDLE (1 << 0)
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-#define AES_REG_SYSSTATUS 0x4C
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-#define AES_REG_SYSSTATUS_RESETDONE (1 << 0)
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+#define AES_REG_LENGTH_N(x) (0x54 + ((x) * 0x04))
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#define DEFAULT_TIMEOUT (5*HZ)
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@@ -72,6 +80,7 @@
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#define FLAGS_ENCRYPT BIT(0)
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#define FLAGS_CBC BIT(1)
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#define FLAGS_GIV BIT(2)
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+#define FLAGS_CTR BIT(3)
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#define FLAGS_INIT BIT(4)
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#define FLAGS_FAST BIT(5)
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@@ -92,11 +101,39 @@ struct omap_aes_reqctx {
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#define OMAP_AES_QUEUE_LENGTH 1
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#define OMAP_AES_CACHE_SIZE 0
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+struct omap_aes_algs_info {
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+ struct crypto_alg *algs_list;
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+ unsigned int size;
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+ unsigned int registered;
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+};
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+
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+struct omap_aes_pdata {
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+ struct omap_aes_algs_info *algs_info;
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+ unsigned int algs_info_size;
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+
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+ void (*trigger)(struct omap_aes_dev *dd, int length);
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+
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+ u32 key_ofs;
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+ u32 iv_ofs;
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+ u32 ctrl_ofs;
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+ u32 data_ofs;
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+ u32 rev_ofs;
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+ u32 mask_ofs;
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+
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+ u32 dma_enable_in;
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+ u32 dma_enable_out;
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+ u32 dma_start;
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+
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+ u32 major_mask;
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+ u32 major_shift;
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+ u32 minor_mask;
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+ u32 minor_shift;
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+};
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+
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struct omap_aes_dev {
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struct list_head list;
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unsigned long phys_base;
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void __iomem *io_base;
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- struct clk *iclk;
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struct omap_aes_ctx *ctx;
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struct device *dev;
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unsigned long flags;
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@@ -111,20 +148,24 @@ struct omap_aes_dev {
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struct ablkcipher_request *req;
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size_t total;
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struct scatterlist *in_sg;
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+ struct scatterlist in_sgl;
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size_t in_offset;
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struct scatterlist *out_sg;
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+ struct scatterlist out_sgl;
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size_t out_offset;
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size_t buflen;
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void *buf_in;
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size_t dma_size;
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int dma_in;
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- int dma_lch_in;
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+ struct dma_chan *dma_lch_in;
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dma_addr_t dma_addr_in;
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void *buf_out;
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int dma_out;
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- int dma_lch_out;
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+ struct dma_chan *dma_lch_out;
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dma_addr_t dma_addr_out;
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+
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+ const struct omap_aes_pdata *pdata;
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};
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/* keep registered devices data here */
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@@ -160,19 +201,6 @@ static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
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omap_aes_write(dd, offset, *value);
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}
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-static int omap_aes_wait(struct omap_aes_dev *dd, u32 offset, u32 bit)
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-{
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- unsigned long timeout = jiffies + DEFAULT_TIMEOUT;
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-
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- while (!(omap_aes_read(dd, offset) & bit)) {
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- if (time_is_before_jiffies(timeout)) {
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- dev_err(dd->dev, "omap-aes timeout\n");
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- return -ETIMEDOUT;
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- }
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- }
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- return 0;
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-}
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-
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static int omap_aes_hw_init(struct omap_aes_dev *dd)
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{
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/*
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@@ -180,23 +208,9 @@ static int omap_aes_hw_init(struct omap_aes_dev *dd)
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* It may be long delays between requests.
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* Device might go to off mode to save power.
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*/
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- clk_enable(dd->iclk);
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+ pm_runtime_get_sync(dd->dev);
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if (!(dd->flags & FLAGS_INIT)) {
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- /* is it necessary to reset before every operation? */
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- omap_aes_write_mask(dd, AES_REG_MASK, AES_REG_MASK_SOFTRESET,
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- AES_REG_MASK_SOFTRESET);
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- /*
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- * prevent OCP bus error (SRESP) in case an access to the module
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- * is performed while the module is coming out of soft reset
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- */
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- __asm__ __volatile__("nop");
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- __asm__ __volatile__("nop");
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-
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- if (omap_aes_wait(dd, AES_REG_SYSSTATUS,
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- AES_REG_SYSSTATUS_RESETDONE))
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- return -ETIMEDOUT;
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-
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dd->flags |= FLAGS_INIT;
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dd->err = 0;
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}
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@@ -208,59 +222,75 @@ static int omap_aes_write_ctrl(struct omap_aes_dev *dd)
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{
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unsigned int key32;
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int i, err;
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- u32 val, mask;
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+ u32 val, mask = 0;
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err = omap_aes_hw_init(dd);
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if (err)
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return err;
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- val = 0;
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- if (dd->dma_lch_out >= 0)
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- val |= AES_REG_MASK_DMA_OUT_EN;
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- if (dd->dma_lch_in >= 0)
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- val |= AES_REG_MASK_DMA_IN_EN;
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-
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- mask = AES_REG_MASK_DMA_IN_EN | AES_REG_MASK_DMA_OUT_EN;
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-
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- omap_aes_write_mask(dd, AES_REG_MASK, val, mask);
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-
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key32 = dd->ctx->keylen / sizeof(u32);
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/* it seems a key should always be set even if it has not changed */
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for (i = 0; i < key32; i++) {
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- omap_aes_write(dd, AES_REG_KEY(i),
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+ omap_aes_write(dd, AES_REG_KEY(dd, i),
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__le32_to_cpu(dd->ctx->key[i]));
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}
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- if ((dd->flags & FLAGS_CBC) && dd->req->info)
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- omap_aes_write_n(dd, AES_REG_IV(0), dd->req->info, 4);
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+ if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info)
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+ omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4);
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val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
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if (dd->flags & FLAGS_CBC)
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val |= AES_REG_CTRL_CBC;
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+ if (dd->flags & FLAGS_CTR) {
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+ val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_32;
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+ mask = AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_MASK;
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+ }
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if (dd->flags & FLAGS_ENCRYPT)
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val |= AES_REG_CTRL_DIRECTION;
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- mask = AES_REG_CTRL_CBC | AES_REG_CTRL_DIRECTION |
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+ mask |= AES_REG_CTRL_CBC | AES_REG_CTRL_DIRECTION |
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AES_REG_CTRL_KEY_SIZE;
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- omap_aes_write_mask(dd, AES_REG_CTRL, val, mask);
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+ omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, mask);
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- /* IN */
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- omap_set_dma_dest_params(dd->dma_lch_in, 0, OMAP_DMA_AMODE_CONSTANT,
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- dd->phys_base + AES_REG_DATA, 0, 4);
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+ return 0;
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+}
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- omap_set_dma_dest_burst_mode(dd->dma_lch_in, OMAP_DMA_DATA_BURST_4);
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- omap_set_dma_src_burst_mode(dd->dma_lch_in, OMAP_DMA_DATA_BURST_4);
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+static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
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+{
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+ u32 mask, val;
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- /* OUT */
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- omap_set_dma_src_params(dd->dma_lch_out, 0, OMAP_DMA_AMODE_CONSTANT,
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- dd->phys_base + AES_REG_DATA, 0, 4);
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+ val = dd->pdata->dma_start;
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- omap_set_dma_src_burst_mode(dd->dma_lch_out, OMAP_DMA_DATA_BURST_4);
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- omap_set_dma_dest_burst_mode(dd->dma_lch_out, OMAP_DMA_DATA_BURST_4);
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+ if (dd->dma_lch_out != NULL)
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+ val |= dd->pdata->dma_enable_out;
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+ if (dd->dma_lch_in != NULL)
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+ val |= dd->pdata->dma_enable_in;
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+
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+ mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
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+ dd->pdata->dma_start;
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+
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+ omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
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- return 0;
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+}
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+
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+static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
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+{
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+ omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
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+ omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
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+
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+ omap_aes_dma_trigger_omap2(dd, length);
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+}
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+
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+static void omap_aes_dma_stop(struct omap_aes_dev *dd)
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+{
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+ u32 mask;
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+
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+ mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
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+ dd->pdata->dma_start;
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+
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+ omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
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}
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static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx)
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@@ -284,18 +314,10 @@ static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx)
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return dd;
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}
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-static void omap_aes_dma_callback(int lch, u16 ch_status, void *data)
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+static void omap_aes_dma_out_callback(void *data)
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{
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struct omap_aes_dev *dd = data;
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- if (ch_status != OMAP_DMA_BLOCK_IRQ) {
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- pr_err("omap-aes DMA error status: 0x%hx\n", ch_status);
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- dd->err = -EIO;
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- dd->flags &= ~FLAGS_INIT; /* request to re-initialize */
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- } else if (lch == dd->dma_lch_in) {
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- return;
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- }
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-
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/* dma_lch_out - completed */
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tasklet_schedule(&dd->done_task);
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}
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@@ -303,9 +325,10 @@ static void omap_aes_dma_callback(int lch, u16 ch_status, void *data)
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static int omap_aes_dma_init(struct omap_aes_dev *dd)
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{
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int err = -ENOMEM;
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+ dma_cap_mask_t mask;
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- dd->dma_lch_out = -1;
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- dd->dma_lch_in = -1;
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+ dd->dma_lch_out = NULL;
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+ dd->dma_lch_in = NULL;
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dd->buf_in = (void *)__get_free_pages(GFP_KERNEL, OMAP_AES_CACHE_SIZE);
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dd->buf_out = (void *)__get_free_pages(GFP_KERNEL, OMAP_AES_CACHE_SIZE);
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@@ -334,23 +357,31 @@ static int omap_aes_dma_init(struct omap_aes_dev *dd)
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goto err_map_out;
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}
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- err = omap_request_dma(dd->dma_in, "omap-aes-rx",
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- omap_aes_dma_callback, dd, &dd->dma_lch_in);
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- if (err) {
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- dev_err(dd->dev, "Unable to request DMA channel\n");
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+ dma_cap_zero(mask);
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+ dma_cap_set(DMA_SLAVE, mask);
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+
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+ dd->dma_lch_in = dma_request_slave_channel_compat(mask,
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+ omap_dma_filter_fn,
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+ &dd->dma_in,
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+ dd->dev, "rx");
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+ if (!dd->dma_lch_in) {
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+ dev_err(dd->dev, "Unable to request in DMA channel\n");
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goto err_dma_in;
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}
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- err = omap_request_dma(dd->dma_out, "omap-aes-tx",
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- omap_aes_dma_callback, dd, &dd->dma_lch_out);
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- if (err) {
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- dev_err(dd->dev, "Unable to request DMA channel\n");
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+
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+ dd->dma_lch_out = dma_request_slave_channel_compat(mask,
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+ omap_dma_filter_fn,
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+ &dd->dma_out,
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+ dd->dev, "tx");
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+ if (!dd->dma_lch_out) {
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+ dev_err(dd->dev, "Unable to request out DMA channel\n");
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goto err_dma_out;
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}
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return 0;
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err_dma_out:
|
|
|
- omap_free_dma(dd->dma_lch_in);
|
|
|
+ dma_release_channel(dd->dma_lch_in);
|
|
|
err_dma_in:
|
|
|
dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen,
|
|
|
DMA_FROM_DEVICE);
|
|
@@ -367,8 +398,8 @@ err_alloc:
|
|
|
|
|
|
static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
|
|
|
{
|
|
|
- omap_free_dma(dd->dma_lch_out);
|
|
|
- omap_free_dma(dd->dma_lch_in);
|
|
|
+ dma_release_channel(dd->dma_lch_out);
|
|
|
+ dma_release_channel(dd->dma_lch_in);
|
|
|
dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen,
|
|
|
DMA_FROM_DEVICE);
|
|
|
dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen, DMA_TO_DEVICE);
|
|
@@ -426,12 +457,15 @@ static int sg_copy(struct scatterlist **sg, size_t *offset, void *buf,
|
|
|
return off;
|
|
|
}
|
|
|
|
|
|
-static int omap_aes_crypt_dma(struct crypto_tfm *tfm, dma_addr_t dma_addr_in,
|
|
|
- dma_addr_t dma_addr_out, int length)
|
|
|
+static int omap_aes_crypt_dma(struct crypto_tfm *tfm,
|
|
|
+ struct scatterlist *in_sg, struct scatterlist *out_sg)
|
|
|
{
|
|
|
struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
|
struct omap_aes_dev *dd = ctx->dd;
|
|
|
- int len32;
|
|
|
+ struct dma_async_tx_descriptor *tx_in, *tx_out;
|
|
|
+ struct dma_slave_config cfg;
|
|
|
+ dma_addr_t dma_addr_in = sg_dma_address(in_sg);
|
|
|
+ int ret, length = sg_dma_len(in_sg);
|
|
|
|
|
|
pr_debug("len: %d\n", length);
|
|
|
|
|
@@ -441,30 +475,61 @@ static int omap_aes_crypt_dma(struct crypto_tfm *tfm, dma_addr_t dma_addr_in,
|
|
|
dma_sync_single_for_device(dd->dev, dma_addr_in, length,
|
|
|
DMA_TO_DEVICE);
|
|
|
|
|
|
- len32 = DIV_ROUND_UP(length, sizeof(u32));
|
|
|
+ memset(&cfg, 0, sizeof(cfg));
|
|
|
+
|
|
|
+ cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
|
|
|
+ cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
|
|
|
+ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
+ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
+ cfg.src_maxburst = DST_MAXBURST;
|
|
|
+ cfg.dst_maxburst = DST_MAXBURST;
|
|
|
|
|
|
/* IN */
|
|
|
- omap_set_dma_transfer_params(dd->dma_lch_in, OMAP_DMA_DATA_TYPE_S32,
|
|
|
- len32, 1, OMAP_DMA_SYNC_PACKET, dd->dma_in,
|
|
|
- OMAP_DMA_DST_SYNC);
|
|
|
+ ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
|
|
|
+ ret);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, 1,
|
|
|
+ DMA_MEM_TO_DEV,
|
|
|
+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
|
+ if (!tx_in) {
|
|
|
+ dev_err(dd->dev, "IN prep_slave_sg() failed\n");
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
|
|
|
- omap_set_dma_src_params(dd->dma_lch_in, 0, OMAP_DMA_AMODE_POST_INC,
|
|
|
- dma_addr_in, 0, 0);
|
|
|
+ /* No callback necessary */
|
|
|
+ tx_in->callback_param = dd;
|
|
|
|
|
|
/* OUT */
|
|
|
- omap_set_dma_transfer_params(dd->dma_lch_out, OMAP_DMA_DATA_TYPE_S32,
|
|
|
- len32, 1, OMAP_DMA_SYNC_PACKET,
|
|
|
- dd->dma_out, OMAP_DMA_SRC_SYNC);
|
|
|
+ ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
|
|
|
+ ret);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, 1,
|
|
|
+ DMA_DEV_TO_MEM,
|
|
|
+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
|
+ if (!tx_out) {
|
|
|
+ dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
|
|
|
- omap_set_dma_dest_params(dd->dma_lch_out, 0, OMAP_DMA_AMODE_POST_INC,
|
|
|
- dma_addr_out, 0, 0);
|
|
|
+ tx_out->callback = omap_aes_dma_out_callback;
|
|
|
+ tx_out->callback_param = dd;
|
|
|
|
|
|
- omap_start_dma(dd->dma_lch_in);
|
|
|
- omap_start_dma(dd->dma_lch_out);
|
|
|
+ dmaengine_submit(tx_in);
|
|
|
+ dmaengine_submit(tx_out);
|
|
|
|
|
|
- /* start DMA or disable idle mode */
|
|
|
- omap_aes_write_mask(dd, AES_REG_MASK, AES_REG_MASK_START,
|
|
|
- AES_REG_MASK_START);
|
|
|
+ dma_async_issue_pending(dd->dma_lch_in);
|
|
|
+ dma_async_issue_pending(dd->dma_lch_out);
|
|
|
+
|
|
|
+ /* start DMA */
|
|
|
+ dd->pdata->trigger(dd, length);
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
@@ -476,6 +541,8 @@ static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
|
|
|
int err, fast = 0, in, out;
|
|
|
size_t count;
|
|
|
dma_addr_t addr_in, addr_out;
|
|
|
+ struct scatterlist *in_sg, *out_sg;
|
|
|
+ int len32;
|
|
|
|
|
|
pr_debug("total: %d\n", dd->total);
|
|
|
|
|
@@ -514,6 +581,9 @@ static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
|
|
|
addr_in = sg_dma_address(dd->in_sg);
|
|
|
addr_out = sg_dma_address(dd->out_sg);
|
|
|
|
|
|
+ in_sg = dd->in_sg;
|
|
|
+ out_sg = dd->out_sg;
|
|
|
+
|
|
|
dd->flags |= FLAGS_FAST;
|
|
|
|
|
|
} else {
|
|
@@ -521,6 +591,27 @@ static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
|
|
|
count = sg_copy(&dd->in_sg, &dd->in_offset, dd->buf_in,
|
|
|
dd->buflen, dd->total, 0);
|
|
|
|
|
|
+ len32 = DIV_ROUND_UP(count, DMA_MIN) * DMA_MIN;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * The data going into the AES module has been copied
|
|
|
+ * to a local buffer and the data coming out will go
|
|
|
+ * into a local buffer so set up local SG entries for
|
|
|
+ * both.
|
|
|
+ */
|
|
|
+ sg_init_table(&dd->in_sgl, 1);
|
|
|
+ dd->in_sgl.offset = dd->in_offset;
|
|
|
+ sg_dma_len(&dd->in_sgl) = len32;
|
|
|
+ sg_dma_address(&dd->in_sgl) = dd->dma_addr_in;
|
|
|
+
|
|
|
+ sg_init_table(&dd->out_sgl, 1);
|
|
|
+ dd->out_sgl.offset = dd->out_offset;
|
|
|
+ sg_dma_len(&dd->out_sgl) = len32;
|
|
|
+ sg_dma_address(&dd->out_sgl) = dd->dma_addr_out;
|
|
|
+
|
|
|
+ in_sg = &dd->in_sgl;
|
|
|
+ out_sg = &dd->out_sgl;
|
|
|
+
|
|
|
addr_in = dd->dma_addr_in;
|
|
|
addr_out = dd->dma_addr_out;
|
|
|
|
|
@@ -530,7 +621,7 @@ static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
|
|
|
|
|
|
dd->total -= count;
|
|
|
|
|
|
- err = omap_aes_crypt_dma(tfm, addr_in, addr_out, count);
|
|
|
+ err = omap_aes_crypt_dma(tfm, in_sg, out_sg);
|
|
|
if (err) {
|
|
|
dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
|
|
|
dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_TO_DEVICE);
|
|
@@ -545,7 +636,7 @@ static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
|
|
|
|
|
|
pr_debug("err: %d\n", err);
|
|
|
|
|
|
- clk_disable(dd->iclk);
|
|
|
+ pm_runtime_put_sync(dd->dev);
|
|
|
dd->flags &= ~FLAGS_BUSY;
|
|
|
|
|
|
req->base.complete(&req->base, err);
|
|
@@ -558,10 +649,10 @@ static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
|
|
|
|
|
|
pr_debug("total: %d\n", dd->total);
|
|
|
|
|
|
- omap_aes_write_mask(dd, AES_REG_MASK, 0, AES_REG_MASK_START);
|
|
|
+ omap_aes_dma_stop(dd);
|
|
|
|
|
|
- omap_stop_dma(dd->dma_lch_in);
|
|
|
- omap_stop_dma(dd->dma_lch_out);
|
|
|
+ dmaengine_terminate_all(dd->dma_lch_in);
|
|
|
+ dmaengine_terminate_all(dd->dma_lch_out);
|
|
|
|
|
|
if (dd->flags & FLAGS_FAST) {
|
|
|
dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
|
|
@@ -734,6 +825,16 @@ static int omap_aes_cbc_decrypt(struct ablkcipher_request *req)
|
|
|
return omap_aes_crypt(req, FLAGS_CBC);
|
|
|
}
|
|
|
|
|
|
+static int omap_aes_ctr_encrypt(struct ablkcipher_request *req)
|
|
|
+{
|
|
|
+ return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
|
|
|
+}
|
|
|
+
|
|
|
+static int omap_aes_ctr_decrypt(struct ablkcipher_request *req)
|
|
|
+{
|
|
|
+ return omap_aes_crypt(req, FLAGS_CTR);
|
|
|
+}
|
|
|
+
|
|
|
static int omap_aes_cra_init(struct crypto_tfm *tfm)
|
|
|
{
|
|
|
pr_debug("enter\n");
|
|
@@ -750,7 +851,7 @@ static void omap_aes_cra_exit(struct crypto_tfm *tfm)
|
|
|
|
|
|
/* ********************** ALGS ************************************ */
|
|
|
|
|
|
-static struct crypto_alg algs[] = {
|
|
|
+static struct crypto_alg algs_ecb_cbc[] = {
|
|
|
{
|
|
|
.cra_name = "ecb(aes)",
|
|
|
.cra_driver_name = "ecb-aes-omap",
|
|
@@ -798,11 +899,213 @@ static struct crypto_alg algs[] = {
|
|
|
}
|
|
|
};
|
|
|
|
|
|
+static struct crypto_alg algs_ctr[] = {
|
|
|
+{
|
|
|
+ .cra_name = "ctr(aes)",
|
|
|
+ .cra_driver_name = "ctr-aes-omap",
|
|
|
+ .cra_priority = 100,
|
|
|
+ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
|
|
|
+ CRYPTO_ALG_KERN_DRIVER_ONLY |
|
|
|
+ CRYPTO_ALG_ASYNC,
|
|
|
+ .cra_blocksize = AES_BLOCK_SIZE,
|
|
|
+ .cra_ctxsize = sizeof(struct omap_aes_ctx),
|
|
|
+ .cra_alignmask = 0,
|
|
|
+ .cra_type = &crypto_ablkcipher_type,
|
|
|
+ .cra_module = THIS_MODULE,
|
|
|
+ .cra_init = omap_aes_cra_init,
|
|
|
+ .cra_exit = omap_aes_cra_exit,
|
|
|
+ .cra_u.ablkcipher = {
|
|
|
+ .min_keysize = AES_MIN_KEY_SIZE,
|
|
|
+ .max_keysize = AES_MAX_KEY_SIZE,
|
|
|
+ .geniv = "eseqiv",
|
|
|
+ .ivsize = AES_BLOCK_SIZE,
|
|
|
+ .setkey = omap_aes_setkey,
|
|
|
+ .encrypt = omap_aes_ctr_encrypt,
|
|
|
+ .decrypt = omap_aes_ctr_decrypt,
|
|
|
+ }
|
|
|
+} ,
|
|
|
+};
|
|
|
+
|
|
|
+static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
|
|
|
+ {
|
|
|
+ .algs_list = algs_ecb_cbc,
|
|
|
+ .size = ARRAY_SIZE(algs_ecb_cbc),
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
|
|
|
+ .algs_info = omap_aes_algs_info_ecb_cbc,
|
|
|
+ .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
|
|
|
+ .trigger = omap_aes_dma_trigger_omap2,
|
|
|
+ .key_ofs = 0x1c,
|
|
|
+ .iv_ofs = 0x20,
|
|
|
+ .ctrl_ofs = 0x30,
|
|
|
+ .data_ofs = 0x34,
|
|
|
+ .rev_ofs = 0x44,
|
|
|
+ .mask_ofs = 0x48,
|
|
|
+ .dma_enable_in = BIT(2),
|
|
|
+ .dma_enable_out = BIT(3),
|
|
|
+ .dma_start = BIT(5),
|
|
|
+ .major_mask = 0xf0,
|
|
|
+ .major_shift = 4,
|
|
|
+ .minor_mask = 0x0f,
|
|
|
+ .minor_shift = 0,
|
|
|
+};
|
|
|
+
|
|
|
+#ifdef CONFIG_OF
|
|
|
+static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
|
|
|
+ {
|
|
|
+ .algs_list = algs_ecb_cbc,
|
|
|
+ .size = ARRAY_SIZE(algs_ecb_cbc),
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .algs_list = algs_ctr,
|
|
|
+ .size = ARRAY_SIZE(algs_ctr),
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
|
|
|
+ .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
|
|
|
+ .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
|
|
|
+ .trigger = omap_aes_dma_trigger_omap2,
|
|
|
+ .key_ofs = 0x1c,
|
|
|
+ .iv_ofs = 0x20,
|
|
|
+ .ctrl_ofs = 0x30,
|
|
|
+ .data_ofs = 0x34,
|
|
|
+ .rev_ofs = 0x44,
|
|
|
+ .mask_ofs = 0x48,
|
|
|
+ .dma_enable_in = BIT(2),
|
|
|
+ .dma_enable_out = BIT(3),
|
|
|
+ .dma_start = BIT(5),
|
|
|
+ .major_mask = 0xf0,
|
|
|
+ .major_shift = 4,
|
|
|
+ .minor_mask = 0x0f,
|
|
|
+ .minor_shift = 0,
|
|
|
+};
|
|
|
+
|
|
|
+static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
|
|
|
+ .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
|
|
|
+ .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
|
|
|
+ .trigger = omap_aes_dma_trigger_omap4,
|
|
|
+ .key_ofs = 0x3c,
|
|
|
+ .iv_ofs = 0x40,
|
|
|
+ .ctrl_ofs = 0x50,
|
|
|
+ .data_ofs = 0x60,
|
|
|
+ .rev_ofs = 0x80,
|
|
|
+ .mask_ofs = 0x84,
|
|
|
+ .dma_enable_in = BIT(5),
|
|
|
+ .dma_enable_out = BIT(6),
|
|
|
+ .major_mask = 0x0700,
|
|
|
+ .major_shift = 8,
|
|
|
+ .minor_mask = 0x003f,
|
|
|
+ .minor_shift = 0,
|
|
|
+};
|
|
|
+
|
|
|
+static const struct of_device_id omap_aes_of_match[] = {
|
|
|
+ {
|
|
|
+ .compatible = "ti,omap2-aes",
|
|
|
+ .data = &omap_aes_pdata_omap2,
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .compatible = "ti,omap3-aes",
|
|
|
+ .data = &omap_aes_pdata_omap3,
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .compatible = "ti,omap4-aes",
|
|
|
+ .data = &omap_aes_pdata_omap4,
|
|
|
+ },
|
|
|
+ {},
|
|
|
+};
|
|
|
+MODULE_DEVICE_TABLE(of, omap_aes_of_match);
|
|
|
+
|
|
|
+static int omap_aes_get_res_of(struct omap_aes_dev *dd,
|
|
|
+ struct device *dev, struct resource *res)
|
|
|
+{
|
|
|
+ struct device_node *node = dev->of_node;
|
|
|
+ const struct of_device_id *match;
|
|
|
+ int err = 0;
|
|
|
+
|
|
|
+ match = of_match_device(of_match_ptr(omap_aes_of_match), dev);
|
|
|
+ if (!match) {
|
|
|
+ dev_err(dev, "no compatible OF match\n");
|
|
|
+ err = -EINVAL;
|
|
|
+ goto err;
|
|
|
+ }
|
|
|
+
|
|
|
+ err = of_address_to_resource(node, 0, res);
|
|
|
+ if (err < 0) {
|
|
|
+ dev_err(dev, "can't translate OF node address\n");
|
|
|
+ err = -EINVAL;
|
|
|
+ goto err;
|
|
|
+ }
|
|
|
+
|
|
|
+ dd->dma_out = -1; /* Dummy value that's unused */
|
|
|
+ dd->dma_in = -1; /* Dummy value that's unused */
|
|
|
+
|
|
|
+ dd->pdata = match->data;
|
|
|
+
|
|
|
+err:
|
|
|
+ return err;
|
|
|
+}
|
|
|
+#else
|
|
|
+static const struct of_device_id omap_aes_of_match[] = {
|
|
|
+ {},
|
|
|
+};
|
|
|
+
|
|
|
+static int omap_aes_get_res_of(struct omap_aes_dev *dd,
|
|
|
+ struct device *dev, struct resource *res)
|
|
|
+{
|
|
|
+ return -EINVAL;
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
|
|
|
+ struct platform_device *pdev, struct resource *res)
|
|
|
+{
|
|
|
+ struct device *dev = &pdev->dev;
|
|
|
+ struct resource *r;
|
|
|
+ int err = 0;
|
|
|
+
|
|
|
+ /* Get the base address */
|
|
|
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
+ if (!r) {
|
|
|
+ dev_err(dev, "no MEM resource info\n");
|
|
|
+ err = -ENODEV;
|
|
|
+ goto err;
|
|
|
+ }
|
|
|
+ memcpy(res, r, sizeof(*res));
|
|
|
+
|
|
|
+ /* Get the DMA out channel */
|
|
|
+ r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
|
|
|
+ if (!r) {
|
|
|
+ dev_err(dev, "no DMA out resource info\n");
|
|
|
+ err = -ENODEV;
|
|
|
+ goto err;
|
|
|
+ }
|
|
|
+ dd->dma_out = r->start;
|
|
|
+
|
|
|
+ /* Get the DMA in channel */
|
|
|
+ r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
|
|
|
+ if (!r) {
|
|
|
+ dev_err(dev, "no DMA in resource info\n");
|
|
|
+ err = -ENODEV;
|
|
|
+ goto err;
|
|
|
+ }
|
|
|
+ dd->dma_in = r->start;
|
|
|
+
|
|
|
+ /* Only OMAP2/3 can be non-DT */
|
|
|
+ dd->pdata = &omap_aes_pdata_omap2;
|
|
|
+
|
|
|
+err:
|
|
|
+ return err;
|
|
|
+}
|
|
|
+
|
|
|
static int omap_aes_probe(struct platform_device *pdev)
|
|
|
{
|
|
|
struct device *dev = &pdev->dev;
|
|
|
struct omap_aes_dev *dd;
|
|
|
- struct resource *res;
|
|
|
+ struct crypto_alg *algp;
|
|
|
+ struct resource res;
|
|
|
int err = -ENOMEM, i, j;
|
|
|
u32 reg;
|
|
|
|
|
@@ -817,49 +1120,31 @@ static int omap_aes_probe(struct platform_device *pdev)
|
|
|
spin_lock_init(&dd->lock);
|
|
|
crypto_init_queue(&dd->queue, OMAP_AES_QUEUE_LENGTH);
|
|
|
|
|
|
- /* Get the base address */
|
|
|
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
- if (!res) {
|
|
|
- dev_err(dev, "invalid resource type\n");
|
|
|
- err = -ENODEV;
|
|
|
- goto err_res;
|
|
|
- }
|
|
|
- dd->phys_base = res->start;
|
|
|
-
|
|
|
- /* Get the DMA */
|
|
|
- res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
|
|
|
- if (!res)
|
|
|
- dev_info(dev, "no DMA info\n");
|
|
|
- else
|
|
|
- dd->dma_out = res->start;
|
|
|
-
|
|
|
- /* Get the DMA */
|
|
|
- res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
|
|
|
- if (!res)
|
|
|
- dev_info(dev, "no DMA info\n");
|
|
|
- else
|
|
|
- dd->dma_in = res->start;
|
|
|
-
|
|
|
- /* Initializing the clock */
|
|
|
- dd->iclk = clk_get(dev, "ick");
|
|
|
- if (IS_ERR(dd->iclk)) {
|
|
|
- dev_err(dev, "clock intialization failed.\n");
|
|
|
- err = PTR_ERR(dd->iclk);
|
|
|
+ err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
|
|
|
+ omap_aes_get_res_pdev(dd, pdev, &res);
|
|
|
+ if (err)
|
|
|
goto err_res;
|
|
|
- }
|
|
|
|
|
|
- dd->io_base = ioremap(dd->phys_base, SZ_4K);
|
|
|
+ dd->io_base = devm_request_and_ioremap(dev, &res);
|
|
|
if (!dd->io_base) {
|
|
|
dev_err(dev, "can't ioremap\n");
|
|
|
err = -ENOMEM;
|
|
|
- goto err_io;
|
|
|
+ goto err_res;
|
|
|
}
|
|
|
+ dd->phys_base = res.start;
|
|
|
+
|
|
|
+ pm_runtime_enable(dev);
|
|
|
+ pm_runtime_get_sync(dev);
|
|
|
+
|
|
|
+ omap_aes_dma_stop(dd);
|
|
|
+
|
|
|
+ reg = omap_aes_read(dd, AES_REG_REV(dd));
|
|
|
+
|
|
|
+ pm_runtime_put_sync(dev);
|
|
|
|
|
|
- clk_enable(dd->iclk);
|
|
|
- reg = omap_aes_read(dd, AES_REG_REV);
|
|
|
dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
|
|
|
- (reg & AES_REG_REV_MAJOR) >> 4, reg & AES_REG_REV_MINOR);
|
|
|
- clk_disable(dd->iclk);
|
|
|
+ (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
|
|
|
+ (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
|
|
|
|
|
|
tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
|
|
|
tasklet_init(&dd->queue_task, omap_aes_queue_task, (unsigned long)dd);
|
|
@@ -873,26 +1158,32 @@ static int omap_aes_probe(struct platform_device *pdev)
|
|
|
list_add_tail(&dd->list, &dev_list);
|
|
|
spin_unlock(&list_lock);
|
|
|
|
|
|
- for (i = 0; i < ARRAY_SIZE(algs); i++) {
|
|
|
- pr_debug("i: %d\n", i);
|
|
|
- err = crypto_register_alg(&algs[i]);
|
|
|
- if (err)
|
|
|
- goto err_algs;
|
|
|
- }
|
|
|
+ for (i = 0; i < dd->pdata->algs_info_size; i++) {
|
|
|
+ for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
|
|
|
+ algp = &dd->pdata->algs_info[i].algs_list[j];
|
|
|
+
|
|
|
+ pr_debug("reg alg: %s\n", algp->cra_name);
|
|
|
+ INIT_LIST_HEAD(&algp->cra_list);
|
|
|
+
|
|
|
+ err = crypto_register_alg(algp);
|
|
|
+ if (err)
|
|
|
+ goto err_algs;
|
|
|
|
|
|
- pr_info("probe() done\n");
|
|
|
+ dd->pdata->algs_info[i].registered++;
|
|
|
+ }
|
|
|
+ }
|
|
|
|
|
|
return 0;
|
|
|
err_algs:
|
|
|
- for (j = 0; j < i; j++)
|
|
|
- crypto_unregister_alg(&algs[j]);
|
|
|
+ for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
|
|
|
+ for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
|
|
|
+ crypto_unregister_alg(
|
|
|
+ &dd->pdata->algs_info[i].algs_list[j]);
|
|
|
omap_aes_dma_cleanup(dd);
|
|
|
err_dma:
|
|
|
tasklet_kill(&dd->done_task);
|
|
|
tasklet_kill(&dd->queue_task);
|
|
|
- iounmap(dd->io_base);
|
|
|
-err_io:
|
|
|
- clk_put(dd->iclk);
|
|
|
+ pm_runtime_disable(dev);
|
|
|
err_res:
|
|
|
kfree(dd);
|
|
|
dd = NULL;
|
|
@@ -904,7 +1195,7 @@ err_data:
|
|
|
static int omap_aes_remove(struct platform_device *pdev)
|
|
|
{
|
|
|
struct omap_aes_dev *dd = platform_get_drvdata(pdev);
|
|
|
- int i;
|
|
|
+ int i, j;
|
|
|
|
|
|
if (!dd)
|
|
|
return -ENODEV;
|
|
@@ -913,33 +1204,52 @@ static int omap_aes_remove(struct platform_device *pdev)
|
|
|
list_del(&dd->list);
|
|
|
spin_unlock(&list_lock);
|
|
|
|
|
|
- for (i = 0; i < ARRAY_SIZE(algs); i++)
|
|
|
- crypto_unregister_alg(&algs[i]);
|
|
|
+ for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
|
|
|
+ for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
|
|
|
+ crypto_unregister_alg(
|
|
|
+ &dd->pdata->algs_info[i].algs_list[j]);
|
|
|
|
|
|
tasklet_kill(&dd->done_task);
|
|
|
tasklet_kill(&dd->queue_task);
|
|
|
omap_aes_dma_cleanup(dd);
|
|
|
- iounmap(dd->io_base);
|
|
|
- clk_put(dd->iclk);
|
|
|
+ pm_runtime_disable(dd->dev);
|
|
|
kfree(dd);
|
|
|
dd = NULL;
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
+#ifdef CONFIG_PM_SLEEP
|
|
|
+static int omap_aes_suspend(struct device *dev)
|
|
|
+{
|
|
|
+ pm_runtime_put_sync(dev);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int omap_aes_resume(struct device *dev)
|
|
|
+{
|
|
|
+ pm_runtime_get_sync(dev);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+static const struct dev_pm_ops omap_aes_pm_ops = {
|
|
|
+ SET_SYSTEM_SLEEP_PM_OPS(omap_aes_suspend, omap_aes_resume)
|
|
|
+};
|
|
|
+
|
|
|
static struct platform_driver omap_aes_driver = {
|
|
|
.probe = omap_aes_probe,
|
|
|
.remove = omap_aes_remove,
|
|
|
.driver = {
|
|
|
.name = "omap-aes",
|
|
|
.owner = THIS_MODULE,
|
|
|
+ .pm = &omap_aes_pm_ops,
|
|
|
+ .of_match_table = omap_aes_of_match,
|
|
|
},
|
|
|
};
|
|
|
|
|
|
static int __init omap_aes_mod_init(void)
|
|
|
{
|
|
|
- pr_info("loading %s driver\n", "omap-aes");
|
|
|
-
|
|
|
return platform_driver_register(&omap_aes_driver);
|
|
|
}
|
|
|
|