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@@ -38,7 +38,7 @@
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/*
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* Get the PHY Chip revision
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*/
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-u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
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+u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band)
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{
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unsigned int i;
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u32 srev;
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@@ -47,11 +47,11 @@ u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
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/*
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* Set the radio chip access register
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*/
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- switch (chan) {
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- case CHANNEL_2GHZ:
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+ switch (band) {
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+ case IEEE80211_BAND_2GHZ:
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ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
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break;
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- case CHANNEL_5GHZ:
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+ case IEEE80211_BAND_5GHZ:
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ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
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break;
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default:
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@@ -84,14 +84,16 @@ u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
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/*
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* Check if a channel is supported
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*/
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-bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
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+bool ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel)
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{
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+ u16 freq = channel->center_freq;
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+
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/* Check if the channel is in our supported range */
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- if (flags & CHANNEL_2GHZ) {
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+ if (channel->band == IEEE80211_BAND_2GHZ) {
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if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
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(freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
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return true;
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- } else if (flags & CHANNEL_5GHZ)
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+ } else if (channel->band == IEEE80211_BAND_5GHZ)
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if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
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(freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
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return true;
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@@ -224,7 +226,7 @@ static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
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ds_coef_exp, ds_coef_man, clock;
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BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
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- !(channel->hw_value & CHANNEL_OFDM));
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+ (channel->hw_value == AR5K_MODE_11B));
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/* Get coefficient
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* ALGO: coef = (5 * clock / carrier_freq) / 2
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@@ -298,7 +300,7 @@ static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah,
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u32 delay;
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delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
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AR5K_PHY_RX_DELAY_M;
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- delay = (channel->hw_value & CHANNEL_CCK) ?
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+ delay = (channel->hw_value == AR5K_MODE_11B) ?
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((delay << 2) / 22) : (delay / 10);
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if (ah->ah_bwmode == AR5K_BWMODE_10MHZ)
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delay = delay << 1;
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@@ -798,9 +800,9 @@ static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
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}
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/* Set Output and Driver bias current (OB/DB) */
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- if (channel->hw_value & CHANNEL_2GHZ) {
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+ if (channel->band == IEEE80211_BAND_2GHZ) {
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- if (channel->hw_value & CHANNEL_CCK)
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+ if (channel->hw_value == AR5K_MODE_11B)
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ee_mode = AR5K_EEPROM_MODE_11B;
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else
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ee_mode = AR5K_EEPROM_MODE_11G;
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@@ -825,7 +827,7 @@ static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
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AR5K_RF_DB_2GHZ, true);
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/* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
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- } else if ((channel->hw_value & CHANNEL_5GHZ) ||
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+ } else if ((channel->band == IEEE80211_BAND_5GHZ) ||
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(ah->ah_radio == AR5K_RF5111)) {
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/* For 11a, Turbo and XR we need to choose
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@@ -857,7 +859,7 @@ static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
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if (ah->ah_radio == AR5K_RF5111) {
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/* Set gain_F settings according to current step */
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- if (channel->hw_value & CHANNEL_OFDM) {
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+ if (channel->hw_value != AR5K_MODE_11B) {
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AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
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AR5K_PHY_FRAME_CTL_TX_CLIP,
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@@ -914,7 +916,7 @@ static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
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if (ah->ah_radio == AR5K_RF5112) {
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/* Set gain_F settings according to current step */
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- if (channel->hw_value & CHANNEL_OFDM) {
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+ if (channel->hw_value != AR5K_MODE_11B) {
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ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
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AR5K_RF_MIXGAIN_OVR, true);
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@@ -1026,7 +1028,7 @@ static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
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}
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if (ah->ah_radio == AR5K_RF5413 &&
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- channel->hw_value & CHANNEL_2GHZ) {
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+ channel->band == IEEE80211_BAND_2GHZ) {
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ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
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true);
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@@ -1138,7 +1140,7 @@ static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
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*/
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data0 = data1 = 0;
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- if (channel->hw_value & CHANNEL_2GHZ) {
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+ if (channel->band == IEEE80211_BAND_2GHZ) {
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/* Map 2GHz channel to 5GHz Atheros channel ID */
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ret = ath5k_hw_rf5111_chan2athchan(
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ieee80211_frequency_to_channel(channel->center_freq),
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@@ -1265,10 +1267,9 @@ static int ath5k_hw_channel(struct ath5k_hw *ah,
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int ret;
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/*
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* Check bounds supported by the PHY (we don't care about regulatory
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- * restrictions at this point). Note: hw_value already has the band
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- * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
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- * of the band by that */
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- if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
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+ * restrictions at this point).
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+ */
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+ if (!ath5k_channel_ok(ah, channel)) {
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ATH5K_ERR(ah,
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"channel frequency (%u MHz) out of supported "
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"band range\n",
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@@ -1614,7 +1615,7 @@ int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
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ret = ath5k_hw_rf511x_iq_calibrate(ah);
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if ((ah->ah_radio == AR5K_RF5111 || ah->ah_radio == AR5K_RF5112) &&
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- (channel->hw_value & CHANNEL_OFDM))
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+ (channel->hw_value != AR5K_MODE_11B))
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ath5k_hw_request_rfgain_probe(ah);
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return ret;
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@@ -1641,7 +1642,7 @@ ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
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/* Convert current frequency to fbin value (the same way channels
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* are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
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* up by 2 so we can compare it later */
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- if (channel->hw_value & CHANNEL_2GHZ) {
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+ if (channel->band == IEEE80211_BAND_2GHZ) {
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chan_fbin = (channel->center_freq - 2300) * 10;
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freq_band = AR5K_EEPROM_BAND_2GHZ;
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} else {
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@@ -1703,7 +1704,7 @@ ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
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spur_freq_sigma_delta = (spur_delta_phase >> 10);
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symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4;
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default:
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- if (channel->hw_value == CHANNEL_A) {
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+ if (channel->band == IEEE80211_BAND_5GHZ) {
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/* Both sample_freq and chip_freq are 40MHz */
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spur_delta_phase = (spur_offset << 17) / 25;
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spur_freq_sigma_delta =
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@@ -2226,15 +2227,20 @@ ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
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idx_l = 0;
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idx_r = 0;
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- if (!(channel->hw_value & CHANNEL_OFDM)) {
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+ switch (channel->hw_value) {
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+ case AR5K_EEPROM_MODE_11A:
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+ pcinfo = ee->ee_pwr_cal_a;
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+ mode = AR5K_EEPROM_MODE_11A;
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+ break;
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+ case AR5K_EEPROM_MODE_11B:
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pcinfo = ee->ee_pwr_cal_b;
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mode = AR5K_EEPROM_MODE_11B;
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- } else if (channel->hw_value & CHANNEL_2GHZ) {
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+ break;
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+ case AR5K_EEPROM_MODE_11G:
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+ default:
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pcinfo = ee->ee_pwr_cal_g;
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mode = AR5K_EEPROM_MODE_11G;
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- } else {
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- pcinfo = ee->ee_pwr_cal_a;
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- mode = AR5K_EEPROM_MODE_11A;
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+ break;
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}
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max = ee->ee_n_piers[mode] - 1;
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@@ -2303,15 +2309,20 @@ ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
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idx_l = 0;
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idx_r = 0;
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- if (!(channel->hw_value & CHANNEL_OFDM)) {
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+ switch (channel->hw_value) {
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+ case AR5K_MODE_11A:
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+ rpinfo = ee->ee_rate_tpwr_a;
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+ mode = AR5K_EEPROM_MODE_11A;
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+ break;
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+ case AR5K_MODE_11B:
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rpinfo = ee->ee_rate_tpwr_b;
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mode = AR5K_EEPROM_MODE_11B;
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- } else if (channel->hw_value & CHANNEL_2GHZ) {
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+ break;
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+ case AR5K_MODE_11G:
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+ default:
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rpinfo = ee->ee_rate_tpwr_g;
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mode = AR5K_EEPROM_MODE_11G;
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- } else {
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- rpinfo = ee->ee_rate_tpwr_a;
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- mode = AR5K_EEPROM_MODE_11A;
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+ break;
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}
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max = ee->ee_rate_target_pwr_num[mode] - 1;
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@@ -2392,20 +2403,20 @@ ath5k_get_max_ctl_power(struct ath5k_hw *ah,
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ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
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- switch (channel->hw_value & CHANNEL_MODES) {
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- case CHANNEL_A:
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+ switch (channel->hw_value) {
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+ case AR5K_MODE_11A:
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if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
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ctl_mode |= AR5K_CTL_TURBO;
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else
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ctl_mode |= AR5K_CTL_11A;
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break;
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- case CHANNEL_G:
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+ case AR5K_MODE_11G:
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if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
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ctl_mode |= AR5K_CTL_TURBOG;
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else
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ctl_mode |= AR5K_CTL_11G;
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break;
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- case CHANNEL_B:
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+ case AR5K_MODE_11B:
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ctl_mode |= AR5K_CTL_11B;
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break;
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default:
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@@ -3290,7 +3301,7 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
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/* Write OFDM timings on 5212*/
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if (ah->ah_version == AR5K_AR5212 &&
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- channel->hw_value & CHANNEL_OFDM) {
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+ channel->hw_value != AR5K_MODE_11B) {
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ret = ath5k_hw_write_ofdm_timings(ah, channel);
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if (ret)
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