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@@ -9239,6 +9239,28 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
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}
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}
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+/* tp->lock is held. */
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+static void tg3_tx_rcbs_disable(struct tg3 *tp)
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+{
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+ u32 txrcb, limit;
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+
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+ /* Disable all transmit rings but the first. */
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+ if (!tg3_flag(tp, 5705_PLUS))
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+ limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
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+ else if (tg3_flag(tp, 5717_PLUS))
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+ limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
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+ else if (tg3_flag(tp, 57765_CLASS) ||
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+ tg3_asic_rev(tp) == ASIC_REV_5762)
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+ limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
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+ else
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+ limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
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+
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+ for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
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+ txrcb < limit; txrcb += TG3_BDINFO_SIZE)
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+ tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
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+ BDINFO_FLAGS_DISABLED);
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+}
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+
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/* tp->lock is held. */
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static void tg3_tx_rcbs_init(struct tg3 *tp)
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{
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@@ -9260,6 +9282,29 @@ static void tg3_tx_rcbs_init(struct tg3 *tp)
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}
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}
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+/* tp->lock is held. */
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+static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
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+{
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+ u32 rxrcb, limit;
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+
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+ /* Disable all receive return rings but the first. */
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+ if (tg3_flag(tp, 5717_PLUS))
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+ limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
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+ else if (!tg3_flag(tp, 5705_PLUS))
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+ limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
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+ else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
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+ tg3_asic_rev(tp) == ASIC_REV_5762 ||
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+ tg3_flag(tp, 57765_CLASS))
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+ limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
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+ else
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+ limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
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+
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+ for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
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+ rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
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+ tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
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+ BDINFO_FLAGS_DISABLED);
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+}
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+
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/* tp->lock is held. */
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static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
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{
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@@ -9285,42 +9330,12 @@ static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
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static void tg3_rings_reset(struct tg3 *tp)
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{
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int i;
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- u32 stblk, txrcb, rxrcb, limit;
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+ u32 stblk;
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struct tg3_napi *tnapi = &tp->napi[0];
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- /* Disable all transmit rings but the first. */
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- if (!tg3_flag(tp, 5705_PLUS))
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- limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
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- else if (tg3_flag(tp, 5717_PLUS))
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- limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
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- else if (tg3_flag(tp, 57765_CLASS) ||
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- tg3_asic_rev(tp) == ASIC_REV_5762)
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- limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
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- else
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- limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
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-
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- for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
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- txrcb < limit; txrcb += TG3_BDINFO_SIZE)
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- tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
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- BDINFO_FLAGS_DISABLED);
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-
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-
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- /* Disable all receive return rings but the first. */
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- if (tg3_flag(tp, 5717_PLUS))
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- limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
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- else if (!tg3_flag(tp, 5705_PLUS))
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- limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
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- else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
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- tg3_asic_rev(tp) == ASIC_REV_5762 ||
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- tg3_flag(tp, 57765_CLASS))
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- limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
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- else
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- limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
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+ tg3_tx_rcbs_disable(tp);
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- for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
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- rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
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- tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
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- BDINFO_FLAGS_DISABLED);
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+ tg3_rx_ret_rcbs_disable(tp);
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/* Disable interrupts */
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tw32_mailbox_f(tp->napi[0].int_mbox, 1);
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