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@@ -2392,7 +2392,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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if (AR_SREV_9280_10_OR_LATER(ah))
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REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
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- if (AR_SREV_9287_10_OR_LATER(ah)) {
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+ if (AR_SREV_9287_12_OR_LATER(ah)) {
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/* Enable ASYNC FIFO */
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REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
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AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
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@@ -2478,7 +2478,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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ath9k_hw_init_user_settings(ah);
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- if (AR_SREV_9287_10_OR_LATER(ah)) {
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+ if (AR_SREV_9287_12_OR_LATER(ah)) {
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REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
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AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
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REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
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@@ -2494,7 +2494,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
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AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
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}
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- if (AR_SREV_9287_10_OR_LATER(ah)) {
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+ if (AR_SREV_9287_12_OR_LATER(ah)) {
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REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
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AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
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}
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