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@@ -730,24 +730,12 @@ static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
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ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
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}
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- if ((ah->ah_radio == AR5K_RF5112) &&
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- (ah->ah_mac_srev < AR5K_SREV_AR5211)) {
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- u32 usec_reg;
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- /* 5311 has different tx/rx latency masks
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- * from 5211, since we deal 5311 the same
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- * as 5211 when setting initvals, shift
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- * values here to their proper locations */
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- usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
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- ath5k_hw_reg_write(ah, usec_reg & (AR5K_USEC_1 |
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- AR5K_USEC_32 |
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- AR5K_USEC_TX_LATENCY_5211 |
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- AR5K_REG_SM(29,
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- AR5K_USEC_RX_LATENCY_5210)),
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- AR5K_USEC_5211);
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+ if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
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/* Clear QCU/DCU clock gating register */
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ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
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/* Set DAC/ADC delays */
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- ath5k_hw_reg_write(ah, 0x08, AR5K_PHY_SCAL);
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+ ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ_5311,
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+ AR5K_PHY_SCAL);
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/* Enable PCU FIFO corruption ECO */
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AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
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AR5K_DIAG_SW_ECO_ENABLE);
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