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@@ -166,9 +166,10 @@ int vid_from_reg(int val, u8 vrm)
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struct vrm_model {
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u8 vendor;
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- u8 eff_family;
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- u8 eff_model;
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- u8 eff_stepping;
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+ u8 family;
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+ u8 model_from;
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+ u8 model_to;
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+ u8 stepping_to;
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u8 vrm_type;
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};
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@@ -177,44 +178,52 @@ struct vrm_model {
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#ifdef CONFIG_X86
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/*
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- * The stepping parameter is highest acceptable stepping for current line.
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+ * The stepping_to parameter is highest acceptable stepping for current line.
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* The model match must be exact for 4-bit values. For model values 0x10
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* and above (extended model), all models below the parameter will match.
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*/
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static struct vrm_model vrm_models[] = {
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- {X86_VENDOR_AMD, 0x6, ANY, ANY, 90}, /* Athlon Duron etc */
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- {X86_VENDOR_AMD, 0xF, 0x3F, ANY, 24}, /* Athlon 64, Opteron */
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+ {X86_VENDOR_AMD, 0x6, 0x0, ANY, ANY, 90}, /* Athlon Duron etc */
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+ {X86_VENDOR_AMD, 0xF, 0x0, 0x3F, ANY, 24}, /* Athlon 64, Opteron */
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/*
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* In theory, all NPT family 0Fh processors have 6 VID pins and should
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* thus use vrm 25, however in practice not all mainboards route the
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* 6th VID pin because it is never needed. So we use the 5 VID pin
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* variant (vrm 24) for the models which exist today.
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*/
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- {X86_VENDOR_AMD, 0xF, 0x7F, ANY, 24}, /* NPT family 0Fh */
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- {X86_VENDOR_AMD, 0xF, ANY, ANY, 25}, /* future fam. 0Fh */
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- {X86_VENDOR_AMD, 0x10, ANY, ANY, 25}, /* NPT family 10h */
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-
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- {X86_VENDOR_INTEL, 0x6, 0x9, ANY, 13}, /* Pentium M (130 nm) */
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- {X86_VENDOR_INTEL, 0x6, 0xB, ANY, 85}, /* Tualatin */
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- {X86_VENDOR_INTEL, 0x6, 0xD, ANY, 13}, /* Pentium M (90 nm) */
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- {X86_VENDOR_INTEL, 0x6, 0xE, ANY, 14}, /* Intel Core (65 nm) */
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- {X86_VENDOR_INTEL, 0x6, 0xF, ANY, 110}, /* Intel Conroe */
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- {X86_VENDOR_INTEL, 0x6, ANY, ANY, 82}, /* any P6 */
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- {X86_VENDOR_INTEL, 0xF, 0x0, ANY, 90}, /* P4 */
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- {X86_VENDOR_INTEL, 0xF, 0x1, ANY, 90}, /* P4 Willamette */
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- {X86_VENDOR_INTEL, 0xF, 0x2, ANY, 90}, /* P4 Northwood */
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- {X86_VENDOR_INTEL, 0xF, ANY, ANY, 100}, /* Prescott and above assume VRD 10 */
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-
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- {X86_VENDOR_CENTAUR, 0x6, 0x7, ANY, 85}, /* Eden ESP/Ezra */
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- {X86_VENDOR_CENTAUR, 0x6, 0x8, 0x7, 85}, /* Ezra T */
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- {X86_VENDOR_CENTAUR, 0x6, 0x9, 0x7, 85}, /* Nehemiah */
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- {X86_VENDOR_CENTAUR, 0x6, 0x9, ANY, 17}, /* C3-M, Eden-N */
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- {X86_VENDOR_CENTAUR, 0x6, 0xA, 0x7, 0}, /* No information */
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- {X86_VENDOR_CENTAUR, 0x6, 0xA, ANY, 13}, /* C7-M, C7, Eden (Esther) */
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- {X86_VENDOR_CENTAUR, 0x6, 0xD, ANY, 134}, /* C7-D, C7-M, C7, Eden (Esther) */
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-
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- {X86_VENDOR_UNKNOWN, ANY, ANY, ANY, 0} /* stop here */
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+ {X86_VENDOR_AMD, 0xF, 0x40, 0x7F, ANY, 24}, /* NPT family 0Fh */
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+ {X86_VENDOR_AMD, 0xF, 0x80, ANY, ANY, 25}, /* future fam. 0Fh */
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+ {X86_VENDOR_AMD, 0x10, 0x0, ANY, ANY, 25}, /* NPT family 10h */
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+
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+ {X86_VENDOR_INTEL, 0x6, 0x0, 0x6, ANY, 82}, /* Pentium Pro,
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+ * Pentium II, Xeon,
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+ * Mobile Pentium,
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+ * Celeron */
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+ {X86_VENDOR_INTEL, 0x6, 0x7, 0x7, ANY, 84}, /* Pentium III, Xeon */
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+ {X86_VENDOR_INTEL, 0x6, 0x8, 0x8, ANY, 82}, /* Pentium III, Xeon */
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+ {X86_VENDOR_INTEL, 0x6, 0x9, 0x9, ANY, 13}, /* Pentium M (130 nm) */
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+ {X86_VENDOR_INTEL, 0x6, 0xA, 0xA, ANY, 82}, /* Pentium III Xeon */
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+ {X86_VENDOR_INTEL, 0x6, 0xB, 0xB, ANY, 85}, /* Tualatin */
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+ {X86_VENDOR_INTEL, 0x6, 0xD, 0xD, ANY, 13}, /* Pentium M (90 nm) */
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+ {X86_VENDOR_INTEL, 0x6, 0xE, 0xE, ANY, 14}, /* Intel Core (65 nm) */
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+ {X86_VENDOR_INTEL, 0x6, 0xF, ANY, ANY, 110}, /* Intel Conroe and
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+ * later */
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+ {X86_VENDOR_INTEL, 0xF, 0x0, 0x0, ANY, 90}, /* P4 */
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+ {X86_VENDOR_INTEL, 0xF, 0x1, 0x1, ANY, 90}, /* P4 Willamette */
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+ {X86_VENDOR_INTEL, 0xF, 0x2, 0x2, ANY, 90}, /* P4 Northwood */
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+ {X86_VENDOR_INTEL, 0xF, 0x3, ANY, ANY, 100}, /* Prescott and above
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+ * assume VRD 10 */
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+
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+ {X86_VENDOR_CENTAUR, 0x6, 0x7, 0x7, ANY, 85}, /* Eden ESP/Ezra */
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+ {X86_VENDOR_CENTAUR, 0x6, 0x8, 0x8, 0x7, 85}, /* Ezra T */
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+ {X86_VENDOR_CENTAUR, 0x6, 0x9, 0x9, 0x7, 85}, /* Nehemiah */
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+ {X86_VENDOR_CENTAUR, 0x6, 0x9, 0x9, ANY, 17}, /* C3-M, Eden-N */
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+ {X86_VENDOR_CENTAUR, 0x6, 0xA, 0xA, 0x7, 0}, /* No information */
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+ {X86_VENDOR_CENTAUR, 0x6, 0xA, 0xA, ANY, 13}, /* C7-M, C7,
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+ * Eden (Esther) */
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+ {X86_VENDOR_CENTAUR, 0x6, 0xD, 0xD, ANY, 134}, /* C7-D, C7-M, C7,
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+ * Eden (Esther) */
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};
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/*
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@@ -250,20 +259,17 @@ static u8 get_via_model_d_vrm(void)
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}
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}
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-static u8 find_vrm(u8 eff_family, u8 eff_model, u8 eff_stepping, u8 vendor)
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+static u8 find_vrm(u8 family, u8 model, u8 stepping, u8 vendor)
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{
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- int i = 0;
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-
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- while (vrm_models[i].vendor!=X86_VENDOR_UNKNOWN) {
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- if (vrm_models[i].vendor==vendor)
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- if ((vrm_models[i].eff_family==eff_family)
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- && ((vrm_models[i].eff_model==eff_model) ||
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- (vrm_models[i].eff_model >= 0x10 &&
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- eff_model <= vrm_models[i].eff_model) ||
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- (vrm_models[i].eff_model==ANY)) &&
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- (eff_stepping <= vrm_models[i].eff_stepping))
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- return vrm_models[i].vrm_type;
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- i++;
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(vrm_models); i++) {
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+ if (vendor == vrm_models[i].vendor &&
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+ family == vrm_models[i].family &&
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+ model >= vrm_models[i].model_from &&
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+ model <= vrm_models[i].model_to &&
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+ stepping <= vrm_models[i].stepping_to)
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+ return vrm_models[i].vrm_type;
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}
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return 0;
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@@ -272,21 +278,12 @@ static u8 find_vrm(u8 eff_family, u8 eff_model, u8 eff_stepping, u8 vendor)
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u8 vid_which_vrm(void)
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{
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struct cpuinfo_x86 *c = &cpu_data(0);
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- u32 eax;
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- u8 eff_family, eff_model, eff_stepping, vrm_ret;
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+ u8 vrm_ret;
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if (c->x86 < 6) /* Any CPU with family lower than 6 */
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- return 0; /* doesn't have VID and/or CPUID */
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-
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- eax = cpuid_eax(1);
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- eff_family = ((eax & 0x00000F00)>>8);
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- eff_model = ((eax & 0x000000F0)>>4);
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- eff_stepping = eax & 0xF;
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- if (eff_family == 0xF) { /* use extended model & family */
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- eff_family += ((eax & 0x00F00000)>>20);
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- eff_model += ((eax & 0x000F0000)>>16)<<4;
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- }
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- vrm_ret = find_vrm(eff_family, eff_model, eff_stepping, c->x86_vendor);
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+ return 0; /* doesn't have VID */
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+
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+ vrm_ret = find_vrm(c->x86, c->x86_model, c->x86_mask, c->x86_vendor);
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if (vrm_ret == 134)
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vrm_ret = get_via_model_d_vrm();
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if (vrm_ret == 0)
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