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@@ -77,13 +77,9 @@ void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
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void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
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{
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u16 ctl, v;
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- int cap, err;
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+ int err;
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- cap = pci_pcie_cap(rdev->pdev);
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- if (!cap)
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- return;
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-
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- err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
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+ err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl);
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if (err)
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return;
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@@ -95,7 +91,7 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
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if ((v == 0) || (v == 6) || (v == 7)) {
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ctl &= ~PCI_EXP_DEVCTL_READRQ;
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ctl |= (2 << 12);
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- pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
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+ pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
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}
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}
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