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@@ -308,9 +308,22 @@ static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height,
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return 0;
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}
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-void viafb_init_accel(struct viafb_shared *shared)
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+int viafb_init_engine(struct fb_info *info)
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{
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- switch (shared->chip_info.gfx_chip_name) {
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+ struct viafb_par *viapar = info->par;
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+ void __iomem *engine;
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+ u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high,
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+ vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name;
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+
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+ engine = ioremap_nocache(info->fix.mmio_start, info->fix.mmio_len);
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+ viapar->shared->engine_mmio = engine;
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+ if (!engine) {
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+ printk(KERN_WARNING "viafb_init_accel: ioremap failed, "
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+ "hardware acceleration disabled\n");
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+ return -ENOMEM;
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+ }
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+
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+ switch (chip_name) {
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case UNICHROME_CLE266:
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case UNICHROME_K400:
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case UNICHROME_K800:
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@@ -321,186 +334,115 @@ void viafb_init_accel(struct viafb_shared *shared)
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case UNICHROME_K8M890:
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case UNICHROME_P4M890:
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case UNICHROME_P4M900:
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- shared->hw_bitblt = hw_bitblt_1;
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+ viapar->shared->hw_bitblt = hw_bitblt_1;
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break;
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case UNICHROME_VX800:
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- shared->hw_bitblt = hw_bitblt_2;
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+ viapar->shared->hw_bitblt = hw_bitblt_2;
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break;
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default:
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- shared->hw_bitblt = NULL;
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+ viapar->shared->hw_bitblt = NULL;
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}
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- viaparinfo->fbmem_free -= CURSOR_SIZE;
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- shared->cursor_vram_addr = viaparinfo->fbmem_free;
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- viaparinfo->fbmem_used += CURSOR_SIZE;
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+ viapar->fbmem_free -= CURSOR_SIZE;
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+ viapar->shared->cursor_vram_addr = viapar->fbmem_free;
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+ viapar->fbmem_used += CURSOR_SIZE;
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- /* Reverse 8*1024 memory space for cursor image */
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- viaparinfo->fbmem_free -= (CURSOR_SIZE + VQ_SIZE);
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- viaparinfo->VQ_start = viaparinfo->fbmem_free;
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- viaparinfo->VQ_end = viaparinfo->VQ_start + VQ_SIZE - 1;
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- viaparinfo->fbmem_used += (CURSOR_SIZE + VQ_SIZE);
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-}
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-
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-void viafb_init_2d_engine(void)
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-{
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- u32 dwVQStartAddr, dwVQEndAddr;
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- u32 dwVQLen, dwVQStartL, dwVQEndL, dwVQStartEndH;
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+ viapar->fbmem_free -= VQ_SIZE;
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+ viapar->shared->vq_vram_addr = viapar->fbmem_free;
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+ viapar->fbmem_used += VQ_SIZE;
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/* Init AGP and VQ regs */
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- switch (viaparinfo->chip_info->gfx_chip_name) {
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+ switch (chip_name) {
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case UNICHROME_K8M890:
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case UNICHROME_P4M900:
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- writel(0x00100000, viaparinfo->io_virt + VIA_REG_CR_TRANSET);
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- writel(0x680A0000, viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
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- writel(0x02000000, viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
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+ writel(0x00100000, engine + VIA_REG_CR_TRANSET);
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+ writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE);
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+ writel(0x02000000, engine + VIA_REG_CR_TRANSPACE);
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break;
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default:
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- writel(0x00100000, viaparinfo->io_virt + VIA_REG_TRANSET);
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- writel(0x00000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x00333004, viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x60000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x61000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x62000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x63000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x64000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x7D000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
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-
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- writel(0xFE020000, viaparinfo->io_virt + VIA_REG_TRANSET);
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- writel(0x00000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
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+ writel(0x00100000, engine + VIA_REG_TRANSET);
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+ writel(0x00000000, engine + VIA_REG_TRANSPACE);
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+ writel(0x00333004, engine + VIA_REG_TRANSPACE);
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+ writel(0x60000000, engine + VIA_REG_TRANSPACE);
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+ writel(0x61000000, engine + VIA_REG_TRANSPACE);
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+ writel(0x62000000, engine + VIA_REG_TRANSPACE);
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+ writel(0x63000000, engine + VIA_REG_TRANSPACE);
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+ writel(0x64000000, engine + VIA_REG_TRANSPACE);
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+ writel(0x7D000000, engine + VIA_REG_TRANSPACE);
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+
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+ writel(0xFE020000, engine + VIA_REG_TRANSET);
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+ writel(0x00000000, engine + VIA_REG_TRANSPACE);
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break;
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}
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- if (viaparinfo->VQ_start != 0) {
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- /* Enable VQ */
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- dwVQStartAddr = viaparinfo->VQ_start;
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- dwVQEndAddr = viaparinfo->VQ_end;
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-
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- dwVQStartL = 0x50000000 | (dwVQStartAddr & 0xFFFFFF);
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- dwVQEndL = 0x51000000 | (dwVQEndAddr & 0xFFFFFF);
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- dwVQStartEndH = 0x52000000 |
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- ((dwVQStartAddr & 0xFF000000) >> 24) |
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- ((dwVQEndAddr & 0xFF000000) >> 16);
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- dwVQLen = 0x53000000 | (VQ_SIZE >> 3);
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- switch (viaparinfo->chip_info->gfx_chip_name) {
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- case UNICHROME_K8M890:
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- case UNICHROME_P4M900:
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- dwVQStartL |= 0x20000000;
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- dwVQEndL |= 0x20000000;
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- dwVQStartEndH |= 0x20000000;
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- dwVQLen |= 0x20000000;
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- break;
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- default:
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- break;
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- }
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- switch (viaparinfo->chip_info->gfx_chip_name) {
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- case UNICHROME_K8M890:
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- case UNICHROME_P4M900:
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- writel(0x00100000,
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- viaparinfo->io_virt + VIA_REG_CR_TRANSET);
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- writel(dwVQStartEndH,
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- viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
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- writel(dwVQStartL,
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- viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
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- writel(dwVQEndL,
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- viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
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- writel(dwVQLen,
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- viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
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- writel(0x74301001,
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- viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
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- writel(0x00000000,
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- viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
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- break;
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- default:
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- writel(0x00FE0000,
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- viaparinfo->io_virt + VIA_REG_TRANSET);
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- writel(0x080003FE,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x0A00027C,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x0B000260,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x0C000274,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x0D000264,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x0E000000,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x0F000020,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x1000027E,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x110002FE,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x200F0060,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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-
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- writel(0x00000006,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x40008C0F,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x44000000,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x45080C04,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x46800408,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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-
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- writel(dwVQStartEndH,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(dwVQStartL,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(dwVQEndL,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(dwVQLen,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- break;
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- }
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- } else {
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- /* Disable VQ */
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- switch (viaparinfo->chip_info->gfx_chip_name) {
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- case UNICHROME_K8M890:
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- case UNICHROME_P4M900:
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- writel(0x00100000,
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- viaparinfo->io_virt + VIA_REG_CR_TRANSET);
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- writel(0x74301000,
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- viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
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- break;
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- default:
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- writel(0x00FE0000,
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- viaparinfo->io_virt + VIA_REG_TRANSET);
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- writel(0x00000004,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x40008C0F,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x44000000,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x45080C04,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- writel(0x46800408,
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- viaparinfo->io_virt + VIA_REG_TRANSPACE);
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- break;
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- }
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+ /* Enable VQ */
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+ vq_start_addr = viapar->shared->vq_vram_addr;
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+ vq_end_addr = viapar->shared->vq_vram_addr + VQ_SIZE - 1;
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+
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+ vq_start_low = 0x50000000 | (vq_start_addr & 0xFFFFFF);
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+ vq_end_low = 0x51000000 | (vq_end_addr & 0xFFFFFF);
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+ vq_high = 0x52000000 | ((vq_start_addr & 0xFF000000) >> 24) |
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+ ((vq_end_addr & 0xFF000000) >> 16);
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+ vq_len = 0x53000000 | (VQ_SIZE >> 3);
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+
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+ switch (chip_name) {
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+ case UNICHROME_K8M890:
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+ case UNICHROME_P4M900:
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+ vq_start_low |= 0x20000000;
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+ vq_end_low |= 0x20000000;
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+ vq_high |= 0x20000000;
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+ vq_len |= 0x20000000;
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+
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+ writel(0x00100000, engine + VIA_REG_CR_TRANSET);
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+ writel(vq_high, engine + VIA_REG_CR_TRANSPACE);
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+ writel(vq_start_low, engine + VIA_REG_CR_TRANSPACE);
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+ writel(vq_end_low, engine + VIA_REG_CR_TRANSPACE);
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+ writel(vq_len, engine + VIA_REG_CR_TRANSPACE);
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+ writel(0x74301001, engine + VIA_REG_CR_TRANSPACE);
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+ writel(0x00000000, engine + VIA_REG_CR_TRANSPACE);
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+ break;
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+ default:
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+ writel(0x00FE0000, engine + VIA_REG_TRANSET);
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+ writel(0x080003FE, engine + VIA_REG_TRANSPACE);
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+ writel(0x0A00027C, engine + VIA_REG_TRANSPACE);
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+ writel(0x0B000260, engine + VIA_REG_TRANSPACE);
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+ writel(0x0C000274, engine + VIA_REG_TRANSPACE);
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+ writel(0x0D000264, engine + VIA_REG_TRANSPACE);
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+ writel(0x0E000000, engine + VIA_REG_TRANSPACE);
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+ writel(0x0F000020, engine + VIA_REG_TRANSPACE);
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+ writel(0x1000027E, engine + VIA_REG_TRANSPACE);
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+ writel(0x110002FE, engine + VIA_REG_TRANSPACE);
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+ writel(0x200F0060, engine + VIA_REG_TRANSPACE);
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+
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+ writel(0x00000006, engine + VIA_REG_TRANSPACE);
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+ writel(0x40008C0F, engine + VIA_REG_TRANSPACE);
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+ writel(0x44000000, engine + VIA_REG_TRANSPACE);
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+ writel(0x45080C04, engine + VIA_REG_TRANSPACE);
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+ writel(0x46800408, engine + VIA_REG_TRANSPACE);
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+
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+ writel(vq_high, engine + VIA_REG_TRANSPACE);
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+ writel(vq_start_low, engine + VIA_REG_TRANSPACE);
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+ writel(vq_end_low, engine + VIA_REG_TRANSPACE);
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+ writel(vq_len, engine + VIA_REG_TRANSPACE);
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+ break;
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}
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-}
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-void viafb_hw_cursor_init(void)
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-{
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/* Set Cursor Image Base Address */
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- writel(viaparinfo->shared->cursor_vram_addr,
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- viaparinfo->io_virt + VIA_REG_CURSOR_MODE);
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- writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_POS);
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- writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_ORG);
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- writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_BG);
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- writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_FG);
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+ writel(viapar->shared->cursor_vram_addr, engine + VIA_REG_CURSOR_MODE);
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+ writel(0x0, engine + VIA_REG_CURSOR_POS);
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+ writel(0x0, engine + VIA_REG_CURSOR_ORG);
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+ writel(0x0, engine + VIA_REG_CURSOR_BG);
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+ writel(0x0, engine + VIA_REG_CURSOR_FG);
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+ return 0;
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}
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void viafb_show_hw_cursor(struct fb_info *info, int Status)
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{
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- u32 temp;
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- u32 iga_path = ((struct viafb_par *)(info->par))->iga_path;
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+ struct viafb_par *viapar = info->par;
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+ u32 temp, iga_path = viapar->iga_path;
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- temp = readl(viaparinfo->io_virt + VIA_REG_CURSOR_MODE);
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+ temp = readl(viapar->shared->engine_mmio + VIA_REG_CURSOR_MODE);
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switch (Status) {
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case HW_Cursor_ON:
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temp |= 0x1;
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@@ -517,25 +459,27 @@ void viafb_show_hw_cursor(struct fb_info *info, int Status)
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default:
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temp &= 0x7FFFFFFF;
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}
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- writel(temp, viaparinfo->io_virt + VIA_REG_CURSOR_MODE);
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+ writel(temp, viapar->shared->engine_mmio + VIA_REG_CURSOR_MODE);
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}
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-int viafb_wait_engine_idle(void)
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+void viafb_wait_engine_idle(struct fb_info *info)
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{
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+ struct viafb_par *viapar = info->par;
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int loop = 0;
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- while (!(readl(viaparinfo->io_virt + VIA_REG_STATUS) &
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+ while (!(readl(viapar->shared->engine_mmio + VIA_REG_STATUS) &
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VIA_VR_QUEUE_BUSY) && (loop < MAXLOOP)) {
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loop++;
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cpu_relax();
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}
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- while ((readl(viaparinfo->io_virt + VIA_REG_STATUS) &
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+ while ((readl(viapar->shared->engine_mmio + VIA_REG_STATUS) &
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(VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)) &&
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(loop < MAXLOOP)) {
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loop++;
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cpu_relax();
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}
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- return loop >= MAXLOOP;
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+ if (loop >= MAXLOOP)
|
|
|
+ printk(KERN_ERR "viafb_wait_engine_idle: not syncing\n");
|
|
|
}
|