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@@ -211,7 +211,7 @@ Channel manager Data Structure entry = 20 DWORD
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#define I2S_TX_CFG 0x0000001A
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#define DEV_CNTRL2 0x00040000
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-#define PCI_INT_MSK 0x00040010
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+
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#define PCI_MSK_APB_DMA (1 << 12)
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#define PCI_MSK_AL_WR (1 << 11)
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#define PCI_MSK_AL_RD (1 << 10)
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@@ -222,6 +222,8 @@ Channel manager Data Structure entry = 20 DWORD
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#define PCI_MSK_VID_C (1 << 2)
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#define PCI_MSK_VID_B (1 << 1)
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#define PCI_MSK_VID_A 1
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+#define PCI_INT_MSK 0x00040010
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+
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#define PCI_INT_STAT 0x00040014
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#define PCI_INT_MSTAT 0x00040018
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@@ -235,7 +237,14 @@ Channel manager Data Structure entry = 20 DWORD
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#define VID_B_INT_MSTAT 0x00040038
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#define VID_B_INT_SSTAT 0x0004003C
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+#define VID_C_MSK_BAD_PKT (1 << 20)
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+#define VID_C_MSK_OPC_ERR (1 << 16)
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+#define VID_C_MSK_SYNC (1 << 12)
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+#define VID_C_MSK_OF (1 << 8)
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+#define VID_C_MSK_RISCI2 (1 << 4)
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+#define VID_C_MSK_RISCI1 1
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#define VID_C_INT_MSK 0x00040040
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+
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#define VID_C_MSK_BAD_PKT (1 << 20)
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#define VID_C_MSK_OPC_ERR (1 << 16)
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#define VID_C_MSK_SYNC (1 << 12)
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