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@@ -38,12 +38,27 @@
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#define MCFINT_UART1 14 /* Interrupt number for UART1 */
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#define MCFINT_UART2 15 /* Interrupt number for UART2 */
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#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
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+#define MCFINT_FECRX0 23 /* Interrupt number for FEC0 */
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+#define MCFINT_FECTX0 27 /* Interrupt number for FEC0 */
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+#define MCFINT_FECENTC0 29 /* Interrupt number for FEC0 */
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#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
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+#define MCFINT2_VECBASE 128 /* Vector base number 2 */
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+#define MCFINT2_FECRX1 23 /* Interrupt number for FEC1 */
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+#define MCFINT2_FECTX1 27 /* Interrupt number for FEC1 */
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+#define MCFINT2_FECENTC1 29 /* Interrupt number for FEC1 */
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+
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#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
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#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
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#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
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+#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
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+#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
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+#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
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+#define MCF_IRQ_FECRX1 (MCFINT2_VECBASE + MCFINT2_FECRX1)
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+#define MCF_IRQ_FECTX1 (MCFINT2_VECBASE + MCFINT2_FECTX1)
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+#define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1)
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+
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/*
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* SDRAM configuration registers.
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*/
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