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@@ -196,14 +196,6 @@
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#define DMA_NONE(args)
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-#define PHYSADDRHI(_pa) (0)
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-#define PHYSADDRHISET(_pa, _val)
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-#define PHYSADDRLO(_pa) ((_pa))
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-#define PHYSADDRLOSET(_pa, _val) \
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- do { \
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- (_pa) = (_val); \
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- } while (0)
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-
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#define d64txregs dregs.d64_u.txregs_64
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#define d64rxregs dregs.d64_u.rxregs_64
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#define txd64 dregs.d64_u.txd_64
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@@ -522,16 +514,14 @@ struct dma_pub *dma_attach(char *name, struct si_pub *sih,
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}
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if ((di->ddoffsetlow != 0) && !di->addrext) {
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- if (PHYSADDRLO(di->txdpa) > SI_PCI_DMA_SZ) {
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+ if (di->txdpa > SI_PCI_DMA_SZ) {
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DMA_ERROR(("%s: dma_attach: txdpa 0x%x: addrext not "
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- "supported\n", di->name,
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- (u32)PHYSADDRLO(di->txdpa)));
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+ "supported\n", di->name, (u32)di->txdpa));
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goto fail;
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}
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- if (PHYSADDRLO(di->rxdpa) > SI_PCI_DMA_SZ) {
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+ if (di->rxdpa > SI_PCI_DMA_SZ) {
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DMA_ERROR(("%s: dma_attach: rxdpa 0x%x: addrext not "
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- "supported\n", di->name,
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- (u32)PHYSADDRLO(di->rxdpa)));
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+ "supported\n", di->name, (u32)di->rxdpa));
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goto fail;
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}
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}
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@@ -586,28 +576,24 @@ dma64_dd_upd(struct dma_info *di, struct dma64desc *ddring,
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/* PCI bus with big(>1G) physical address, use address extension */
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#if defined(__mips__) && defined(IL_BIGENDIAN)
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if ((di->dataoffsetlow == SI_SDRAM_SWAPPED)
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- || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
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+ || !(pa & PCI32ADDR_HIGH)) {
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#else
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- if ((di->dataoffsetlow == 0) || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
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+ if ((di->dataoffsetlow == 0) || !(pa & PCI32ADDR_HIGH)) {
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#endif /* defined(__mips__) && defined(IL_BIGENDIAN) */
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- ddring[outidx].addrlow =
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- BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow);
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- ddring[outidx].addrhigh =
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- BUS_SWAP32(PHYSADDRHI(pa) + di->dataoffsethigh);
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+ ddring[outidx].addrlow = BUS_SWAP32(pa + di->dataoffsetlow);
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+ ddring[outidx].addrhigh = BUS_SWAP32(di->dataoffsethigh);
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ddring[outidx].ctrl1 = BUS_SWAP32(*flags);
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ddring[outidx].ctrl2 = BUS_SWAP32(ctrl2);
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} else {
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/* address extension for 32-bit PCI */
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u32 ae;
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- ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
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- PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
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+ ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
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+ pa &= ~PCI32ADDR_HIGH;
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ctrl2 |= (ae << D64_CTRL2_AE_SHIFT) & D64_CTRL2_AE;
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- ddring[outidx].addrlow =
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- BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow);
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- ddring[outidx].addrhigh =
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- BUS_SWAP32(0 + di->dataoffsethigh);
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+ ddring[outidx].addrlow = BUS_SWAP32(pa + di->dataoffsetlow);
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+ ddring[outidx].addrhigh = BUS_SWAP32(di->dataoffsethigh);
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ddring[outidx].ctrl1 = BUS_SWAP32(*flags);
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ddring[outidx].ctrl2 = BUS_SWAP32(ctrl2);
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}
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@@ -716,45 +702,36 @@ _dma_ddtable_init(struct dma_info *di, uint direction, unsigned long pa)
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{
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if (!di->aligndesc_4k) {
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if (direction == DMA_TX)
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- di->xmtptrbase = PHYSADDRLO(pa);
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+ di->xmtptrbase = pa;
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else
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- di->rcvptrbase = PHYSADDRLO(pa);
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+ di->rcvptrbase = pa;
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}
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if ((di->ddoffsetlow == 0)
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- || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
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+ || !(pa & PCI32ADDR_HIGH)) {
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if (direction == DMA_TX) {
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- W_REG(&di->d64txregs->addrlow,
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- (PHYSADDRLO(pa) + di->ddoffsetlow));
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- W_REG(&di->d64txregs->addrhigh,
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- (PHYSADDRHI(pa) + di->ddoffsethigh));
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+ W_REG(&di->d64txregs->addrlow, pa + di->ddoffsetlow);
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+ W_REG(&di->d64txregs->addrhigh, di->ddoffsethigh);
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} else {
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- W_REG(&di->d64rxregs->addrlow,
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- (PHYSADDRLO(pa) + di->ddoffsetlow));
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- W_REG(&di->d64rxregs->addrhigh,
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- (PHYSADDRHI(pa) + di->ddoffsethigh));
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+ W_REG(&di->d64rxregs->addrlow, pa + di->ddoffsetlow);
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+ W_REG(&di->d64rxregs->addrhigh, di->ddoffsethigh);
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}
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} else {
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/* DMA64 32bits address extension */
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u32 ae;
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/* shift the high bit(s) from pa to ae */
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- ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >>
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- PCI32ADDR_HIGH_SHIFT;
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- PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
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+ ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
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+ pa &= ~PCI32ADDR_HIGH;
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if (direction == DMA_TX) {
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- W_REG(&di->d64txregs->addrlow,
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- (PHYSADDRLO(pa) + di->ddoffsetlow));
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- W_REG(&di->d64txregs->addrhigh,
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- di->ddoffsethigh);
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+ W_REG(&di->d64txregs->addrlow, pa + di->ddoffsetlow);
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+ W_REG(&di->d64txregs->addrhigh, di->ddoffsethigh);
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SET_REG(&di->d64txregs->control,
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D64_XC_AE, (ae << D64_XC_AE_SHIFT));
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} else {
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- W_REG(&di->d64rxregs->addrlow,
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- (PHYSADDRLO(pa) + di->ddoffsetlow));
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- W_REG(&di->d64rxregs->addrhigh,
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- di->ddoffsethigh);
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+ W_REG(&di->d64rxregs->addrlow, pa + di->ddoffsetlow);
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+ W_REG(&di->d64rxregs->addrhigh, di->ddoffsethigh);
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SET_REG(&di->d64rxregs->control,
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D64_RC_AE, (ae << D64_RC_AE_SHIFT));
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}
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@@ -1196,9 +1173,7 @@ static bool dma64_alloc(struct dma_info *di, uint direction)
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di->txd64 = (struct dma64desc *)
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roundup((unsigned long)va, align);
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di->txdalign = (uint) ((s8 *)di->txd64 - (s8 *) va);
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- PHYSADDRLOSET(di->txdpa,
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- PHYSADDRLO(di->txdpaorig) + di->txdalign);
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- PHYSADDRHISET(di->txdpa, PHYSADDRHI(di->txdpaorig));
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+ di->txdpa = di->txdpaorig + di->txdalign;
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di->txdalloc = alloced;
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} else {
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va = dma_ringalloc(di, D64RINGALIGN, size, &align_bits,
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@@ -1212,9 +1187,7 @@ static bool dma64_alloc(struct dma_info *di, uint direction)
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di->rxd64 = (struct dma64desc *)
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roundup((unsigned long)va, align);
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di->rxdalign = (uint) ((s8 *)di->rxd64 - (s8 *) va);
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- PHYSADDRLOSET(di->rxdpa,
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- PHYSADDRLO(di->rxdpaorig) + di->rxdalign);
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- PHYSADDRHISET(di->rxdpa, PHYSADDRHI(di->rxdpaorig));
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+ di->rxdpa = di->rxdpaorig + di->rxdalign;
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di->rxdalloc = alloced;
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}
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@@ -1451,12 +1424,7 @@ struct sk_buff *dma_getnexttxp(struct dma_pub *pub, enum txd_range range)
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struct dma_seg_map *map = NULL;
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uint size, j, nsegs;
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- PHYSADDRLOSET(pa,
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- (BUS_SWAP32(di->txd64[i].addrlow) -
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- di->dataoffsetlow));
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- PHYSADDRHISET(pa,
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- (BUS_SWAP32(di->txd64[i].addrhigh) -
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- di->dataoffsethigh));
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+ pa = BUS_SWAP32(di->txd64[i].addrlow) - di->dataoffsetlow;
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if (DMASGLIST_ENAB) {
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map = &di->txp_dmah[i];
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@@ -1519,12 +1487,7 @@ static struct sk_buff *dma64_getnextrxp(struct dma_info *di, bool forceall)
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rxp = di->rxp[i];
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di->rxp[i] = NULL;
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- PHYSADDRLOSET(pa,
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- (BUS_SWAP32(di->rxd64[i].addrlow) -
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- di->dataoffsetlow));
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- PHYSADDRHISET(pa,
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- (BUS_SWAP32(di->rxd64[i].addrhigh) -
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- di->dataoffsethigh));
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+ pa = BUS_SWAP32(di->rxd64[i].addrlow) - di->dataoffsetlow;
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/* clear this packet from the descriptor ring */
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pci_unmap_single(di->pbus, pa, di->rxbufsize, PCI_DMA_FROMDEVICE);
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