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@@ -136,6 +136,8 @@ static char mv643xx_eth_driver_version[] = "1.4";
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#define INT_MASK 0x0068
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#define INT_MASK_EXT 0x006c
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#define TX_FIFO_URGENT_THRESHOLD 0x0074
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+#define RX_DISCARD_FRAME_CNT 0x0084
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+#define RX_OVERRUN_FRAME_CNT 0x0088
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#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
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#define TX_BW_RATE_MOVED 0x00e0
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#define TX_BW_MTU_MOVED 0x00e8
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@@ -334,6 +336,9 @@ struct mib_counters {
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u32 bad_crc_event;
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u32 collision;
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u32 late_collision;
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+ /* Non MIB hardware counters */
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+ u32 rx_discard;
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+ u32 rx_overrun;
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};
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struct lro_counters {
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@@ -1225,6 +1230,10 @@ static void mib_counters_clear(struct mv643xx_eth_private *mp)
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for (i = 0; i < 0x80; i += 4)
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mib_read(mp, i);
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+
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+ /* Clear non MIB hw counters also */
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+ rdlp(mp, RX_DISCARD_FRAME_CNT);
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+ rdlp(mp, RX_OVERRUN_FRAME_CNT);
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}
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static void mib_counters_update(struct mv643xx_eth_private *mp)
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@@ -1262,6 +1271,9 @@ static void mib_counters_update(struct mv643xx_eth_private *mp)
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p->bad_crc_event += mib_read(mp, 0x74);
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p->collision += mib_read(mp, 0x78);
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p->late_collision += mib_read(mp, 0x7c);
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+ /* Non MIB hardware counters */
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+ p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
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+ p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
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spin_unlock_bh(&mp->mib_counters_lock);
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mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
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@@ -1413,6 +1425,8 @@ static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
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MIBSTAT(bad_crc_event),
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MIBSTAT(collision),
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MIBSTAT(late_collision),
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+ MIBSTAT(rx_discard),
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+ MIBSTAT(rx_overrun),
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LROSTAT(lro_aggregated),
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LROSTAT(lro_flushed),
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LROSTAT(lro_no_desc),
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