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@@ -49,6 +49,8 @@
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#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
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#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
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#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
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+#define INTCPS_NR_MIR_REGS 3
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+#define INTCPS_NR_IRQS 96
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/*
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* OMAP2 has a number of different interrupt controllers, each interrupt
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