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@@ -151,24 +151,8 @@ typedef struct dma_info {
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bool aligndesc_4k; /* descriptor base need to be aligned or not */
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} dma_info_t;
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-/*
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- * If BCMDMA32 is defined, hnddma will support both 32-bit and 64-bit DMA engines.
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- * Otherwise it will support only 64-bit.
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- *
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- * DMA32_ENAB indicates whether hnddma is compiled with support for 32-bit DMA engines.
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- * DMA64_ENAB indicates whether hnddma is compiled with support for 64-bit DMA engines.
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- *
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- * DMA64_MODE indicates whether the current DMA engine is running as 64-bit.
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- */
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-#ifdef BCMDMA32
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-#define DMA32_ENAB(di) 1
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-#define DMA64_ENAB(di) 1
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-#define DMA64_MODE(di) ((di)->dma64)
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-#else /* !BCMDMA32 */
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-#define DMA32_ENAB(di) 0
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#define DMA64_ENAB(di) 1
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#define DMA64_MODE(di) 1
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-#endif /* !BCMDMA32 */
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/* DMA Scatter-gather list is supported. Note this is limited to TX direction only */
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#ifdef BCMDMASGLISTOSL
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@@ -418,12 +402,6 @@ struct hnddma_pub *dma_attach(struct osl_info *osh, char *name, si_t *sih,
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di->d64txregs = (dma64regs_t *) dmaregstx;
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di->d64rxregs = (dma64regs_t *) dmaregsrx;
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di->hnddma.di_fn = (const di_fcn_t *)&dma64proc;
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- } else if (DMA32_ENAB(di)) {
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- ASSERT(ntxd <= D32MAXDD);
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- ASSERT(nrxd <= D32MAXDD);
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- di->d32txregs = (dma32regs_t *) dmaregstx;
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- di->d32rxregs = (dma32regs_t *) dmaregsrx;
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- di->hnddma.di_fn = (const di_fcn_t *)&dma32proc;
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} else {
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DMA_ERROR(("dma_attach: driver doesn't support 32-bit DMA\n"));
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ASSERT(0);
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@@ -683,8 +661,6 @@ static bool _dma_alloc(dma_info_t *di, uint direction)
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{
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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return dma64_alloc(di, direction);
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- } else if (DMA32_ENAB(di)) {
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- return dma32_alloc(di, direction);
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} else
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ASSERT(0);
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}
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@@ -711,17 +687,6 @@ static void _dma_detach(dma_info_t *di)
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((s8 *)di->rxd64 -
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di->rxdalign), di->rxdalloc,
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(di->rxdpaorig), &di->rx_dmah);
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- } else if (DMA32_ENAB(di)) {
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- if (di->txd32)
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- DMA_FREE_CONSISTENT(di->osh,
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- ((s8 *)di->txd32 -
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- di->txdalign), di->txdalloc,
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- (di->txdpaorig), &di->tx_dmah);
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- if (di->rxd32)
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- DMA_FREE_CONSISTENT(di->osh,
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- ((s8 *)di->rxd32 -
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- di->rxdalign), di->rxdalloc,
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- (di->rxdpaorig), &di->rx_dmah);
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} else
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ASSERT(0);
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@@ -786,11 +751,6 @@ static bool _dma_isaddrext(dma_info_t *di)
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return true;
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}
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return false;
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- } else if (DMA32_ENAB(di)) {
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- if (di->d32txregs)
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- return _dma32_addrext(di->osh, di->d32txregs);
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- else if (di->d32rxregs)
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- return _dma32_addrext(di->osh, di->d32rxregs);
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} else
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ASSERT(0);
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@@ -848,39 +808,6 @@ static void _dma_ddtable_init(dma_info_t *di, uint direction, dmaaddr_t pa)
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D64_RC_AE, (ae << D64_RC_AE_SHIFT));
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}
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}
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-
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- } else if (DMA32_ENAB(di)) {
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- ASSERT(PHYSADDRHI(pa) == 0);
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- if ((di->ddoffsetlow == 0)
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- || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
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- if (direction == DMA_TX)
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- W_REG(di->osh, &di->d32txregs->addr,
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- (PHYSADDRLO(pa) + di->ddoffsetlow));
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- else
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- W_REG(di->osh, &di->d32rxregs->addr,
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- (PHYSADDRLO(pa) + di->ddoffsetlow));
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- } else {
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- /* dma32 address extension */
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- u32 ae;
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- ASSERT(di->addrext);
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-
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- /* shift the high bit(s) from pa to ae */
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- ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >>
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- PCI32ADDR_HIGH_SHIFT;
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- PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
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-
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- if (direction == DMA_TX) {
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- W_REG(di->osh, &di->d32txregs->addr,
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- (PHYSADDRLO(pa) + di->ddoffsetlow));
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- SET_REG(di->osh, &di->d32txregs->control, XC_AE,
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- ae << XC_AE_SHIFT);
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- } else {
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- W_REG(di->osh, &di->d32rxregs->addr,
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- (PHYSADDRLO(pa) + di->ddoffsetlow));
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- SET_REG(di->osh, &di->d32rxregs->control, RC_AE,
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- ae << RC_AE_SHIFT);
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- }
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- }
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} else
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ASSERT(0);
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}
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@@ -891,8 +818,6 @@ static void _dma_fifoloopbackenable(dma_info_t *di)
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if (DMA64_ENAB(di) && DMA64_MODE(di))
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OR_REG(di->osh, &di->d64txregs->control, D64_XC_LE);
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- else if (DMA32_ENAB(di))
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- OR_REG(di->osh, &di->d32txregs->control, XC_LE);
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else
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ASSERT(0);
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}
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@@ -921,11 +846,6 @@ static void _dma_rxinit(dma_info_t *di)
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if (di->aligndesc_4k)
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_dma_ddtable_init(di, DMA_RX, di->rxdpa);
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- } else if (DMA32_ENAB(di)) {
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- memset((void *)di->rxd32, '\0',
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- (di->nrxd * sizeof(dma32dd_t)));
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- _dma_rxenable(di);
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- _dma_ddtable_init(di, DMA_RX, di->rxdpa);
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} else
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ASSERT(0);
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}
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@@ -949,18 +869,6 @@ static void _dma_rxenable(dma_info_t *di)
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W_REG(di->osh, &di->d64rxregs->control,
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((di->rxoffset << D64_RC_RO_SHIFT) | control));
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- } else if (DMA32_ENAB(di)) {
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- u32 control =
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- (R_REG(di->osh, &di->d32rxregs->control) & RC_AE) | RC_RE;
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-
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- if ((dmactrlflags & DMA_CTRL_PEN) == 0)
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- control |= RC_PD;
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-
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- if (dmactrlflags & DMA_CTRL_ROC)
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- control |= RC_OC;
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-
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- W_REG(di->osh, &di->d32rxregs->control,
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- ((di->rxoffset << RC_RO_SHIFT) | control));
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} else
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ASSERT(0);
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}
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@@ -1103,11 +1011,6 @@ static bool BCMFASTPATH _dma_rxfill(dma_info_t *di)
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DMA_ERROR(("%s: rxfill64: ring is empty !\n", di->name));
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ring_empty = true;
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}
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- } else if (DMA32_ENAB(di)) {
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- if (dma32_rxidle(di)) {
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- DMA_ERROR(("%s: rxfill32: ring is empty !\n", di->name));
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- ring_empty = true;
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- }
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} else
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ASSERT(0);
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}
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@@ -1144,13 +1047,6 @@ static bool BCMFASTPATH _dma_rxfill(dma_info_t *di)
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dma64_dd_upd(di, di->rxd64, pa, rxout, &flags,
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di->rxbufsize);
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- } else if (DMA32_ENAB(di)) {
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- if (rxout == (di->nrxd - 1))
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- flags = CTRL_EOT;
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-
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- ASSERT(PHYSADDRHI(pa) == 0);
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- dma32_dd_upd(di, di->rxd32, pa, rxout, &flags,
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- di->rxbufsize);
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} else
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ASSERT(0);
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rxout = NEXTRXD(rxout);
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@@ -1162,8 +1058,6 @@ static bool BCMFASTPATH _dma_rxfill(dma_info_t *di)
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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W_REG(di->osh, &di->d64rxregs->ptr,
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di->rcvptrbase + I2B(rxout, dma64dd_t));
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- } else if (DMA32_ENAB(di)) {
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- W_REG(di->osh, &di->d32rxregs->ptr, I2B(rxout, dma32dd_t));
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} else
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ASSERT(0);
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@@ -1183,10 +1077,6 @@ static void *_dma_peeknexttxp(dma_info_t *di)
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B2I(((R_REG(di->osh, &di->d64txregs->status0) &
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D64_XS0_CD_MASK) - di->xmtptrbase) & D64_XS0_CD_MASK,
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dma64dd_t);
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- } else if (DMA32_ENAB(di)) {
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- end =
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- B2I(R_REG(di->osh, &di->d32txregs->status) & XS_CD_MASK,
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- dma32dd_t);
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} else
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ASSERT(0);
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@@ -1210,10 +1100,6 @@ static void *_dma_peeknextrxp(dma_info_t *di)
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B2I(((R_REG(di->osh, &di->d64rxregs->status0) &
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D64_RS0_CD_MASK) - di->rcvptrbase) & D64_RS0_CD_MASK,
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dma64dd_t);
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- } else if (DMA32_ENAB(di)) {
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- end =
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- B2I(R_REG(di->osh, &di->d32rxregs->status) & RS_CD_MASK,
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- dma32dd_t);
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} else
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ASSERT(0);
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@@ -1241,8 +1127,6 @@ static void *BCMFASTPATH _dma_getnextrxp(dma_info_t *di, bool forceall)
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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return dma64_getnextrxp(di, forceall);
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- } else if (DMA32_ENAB(di)) {
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- return dma32_getnextrxp(di, forceall);
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} else
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ASSERT(0);
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}
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@@ -1271,10 +1155,6 @@ static uint _dma_txpending(dma_info_t *di)
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B2I(((R_REG(di->osh, &di->d64txregs->status0) &
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D64_XS0_CD_MASK) - di->xmtptrbase) & D64_XS0_CD_MASK,
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dma64dd_t);
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- } else if (DMA32_ENAB(di)) {
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- curr =
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- B2I(R_REG(di->osh, &di->d32txregs->status) & XS_CD_MASK,
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- dma32dd_t);
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} else
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ASSERT(0);
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@@ -1291,8 +1171,6 @@ static uint _dma_txcommitted(dma_info_t *di)
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if (DMA64_ENAB(di) && DMA64_MODE(di)) {
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ptr = B2I(R_REG(di->osh, &di->d64txregs->ptr), dma64dd_t);
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- } else if (DMA32_ENAB(di)) {
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- ptr = B2I(R_REG(di->osh, &di->d32txregs->ptr), dma32dd_t);
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} else
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ASSERT(0);
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@@ -1344,17 +1222,6 @@ static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags)
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/* Not supported, don't allow it to be enabled */
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dmactrlflags &= ~DMA_CTRL_PEN;
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}
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- } else if (DMA32_ENAB(di)) {
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- control = R_REG(di->osh, &di->d32txregs->control);
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- W_REG(di->osh, &di->d32txregs->control,
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- control | XC_PD);
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- if (R_REG(di->osh, &di->d32txregs->control) & XC_PD) {
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- W_REG(di->osh, &di->d32txregs->control,
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- control);
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- } else {
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- /* Not supported, don't allow it to be enabled */
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- dmactrlflags &= ~DMA_CTRL_PEN;
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- }
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} else
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ASSERT(0);
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}
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