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@@ -130,25 +130,6 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
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rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay);
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}
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-static void rcar_du_crtc_set_routing(struct rcar_du_crtc *rcrtc)
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-{
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- struct rcar_du_device *rcdu = rcrtc->group->dev;
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- u32 dorcr = rcar_du_read(rcdu, DORCR);
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-
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- dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);
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-
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- /* Set the DU1 pins sources. Select CRTC 0 if explicitly requested and
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- * CRTC 1 in all other cases to avoid cloning CRTC 0 to DU0 and DU1 by
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- * default.
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- */
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- if (rcrtc->outputs & (1 << 1) && rcrtc->index == 0)
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- dorcr |= DORCR_PG2D_DS1;
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- else
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- dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2;
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-
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- rcar_du_write(rcdu, DORCR, dorcr);
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-}
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-
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void rcar_du_crtc_route_output(struct drm_crtc *crtc, unsigned int output)
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{
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struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
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@@ -245,7 +226,7 @@ static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
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/* Configure display timings and output routing */
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rcar_du_crtc_set_display_timing(rcrtc);
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- rcar_du_crtc_set_routing(rcrtc);
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+ rcar_du_group_set_routing(rcrtc->group);
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mutex_lock(&rcrtc->group->planes.lock);
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rcrtc->plane->enabled = true;
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