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@@ -565,6 +565,19 @@ static void sil_freeze(struct ata_port *ap)
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tmp |= SIL_MASK_IDE0_INT << ap->port_no;
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writel(tmp, mmio_base + SIL_SYSCFG);
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readl(mmio_base + SIL_SYSCFG); /* flush */
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+
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+ /* Ensure DMA_ENABLE is off.
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+ *
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+ * This is because the controller will not give us access to the
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+ * taskfile registers while a DMA is in progress
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+ */
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+ iowrite8(ioread8(ap->ioaddr.bmdma_addr) & ~SIL_DMA_ENABLE,
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+ ap->ioaddr.bmdma_addr);
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+
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+ /* According to ata_bmdma_stop, an HDMA transition requires
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+ * on PIO cycle. But we can't read a taskfile register.
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+ */
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+ ioread8(ap->ioaddr.bmdma_addr);
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}
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static void sil_thaw(struct ata_port *ap)
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