|
@@ -72,8 +72,9 @@
|
|
|
#define BM_TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
|
|
|
#define BM_TIMROT_TIMCTRLn_IRQ (1 << 15)
|
|
|
#define BP_TIMROT_TIMCTRLn_SELECT 0
|
|
|
-#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
|
|
|
-#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
|
|
|
+#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
|
|
|
+#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
|
|
|
+#define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS 0xf
|
|
|
|
|
|
static struct clock_event_device mxs_clockevent_device;
|
|
|
static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
|
|
@@ -274,7 +275,7 @@ void __init mxs_timer_init(void)
|
|
|
/* one for clock_event */
|
|
|
__raw_writel((timrot_is_v1() ?
|
|
|
BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
|
|
|
- BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
|
|
|
+ BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
|
|
|
BM_TIMROT_TIMCTRLn_UPDATE |
|
|
|
BM_TIMROT_TIMCTRLn_IRQ_EN,
|
|
|
mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
|
|
@@ -282,7 +283,7 @@ void __init mxs_timer_init(void)
|
|
|
/* another for clocksource */
|
|
|
__raw_writel((timrot_is_v1() ?
|
|
|
BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
|
|
|
- BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
|
|
|
+ BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
|
|
|
BM_TIMROT_TIMCTRLn_RELOAD,
|
|
|
mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
|
|
|
|