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@@ -993,7 +993,7 @@ static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
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int nouveau_load(struct drm_device *dev, unsigned long flags)
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{
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struct drm_nouveau_private *dev_priv;
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- uint32_t reg0, strap;
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+ uint32_t reg0 = ~0, strap;
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resource_size_t mmio_start_offs;
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int ret;
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@@ -1012,10 +1012,65 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
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NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
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dev->pci_vendor, dev->pci_device, dev->pdev->class);
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- /* resource 0 is mmio regs */
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- /* resource 1 is linear FB */
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- /* resource 2 is RAMIN (mmio regs + 0x1000000) */
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- /* resource 6 is bios */
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+ /* first up, map the start of mmio and determine the chipset */
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+ dev_priv->mmio = ioremap(pci_resource_start(dev->pdev, 0), PAGE_SIZE);
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+ if (dev_priv->mmio) {
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+#ifdef __BIG_ENDIAN
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+ /* put the card into big-endian mode if it's not */
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+ if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
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+ nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
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+ DRM_MEMORYBARRIER();
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+#endif
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+
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+ /* determine chipset and derive architecture from it */
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+ reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
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+ if ((reg0 & 0x0f000000) > 0) {
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+ dev_priv->chipset = (reg0 & 0xff00000) >> 20;
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+ switch (dev_priv->chipset & 0xf0) {
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+ case 0x10:
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+ case 0x20:
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+ case 0x30:
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+ dev_priv->card_type = dev_priv->chipset & 0xf0;
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+ break;
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+ case 0x40:
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+ case 0x60:
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+ dev_priv->card_type = NV_40;
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+ break;
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+ case 0x50:
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+ case 0x80:
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+ case 0x90:
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+ case 0xa0:
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+ dev_priv->card_type = NV_50;
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+ break;
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+ case 0xc0:
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+ dev_priv->card_type = NV_C0;
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+ break;
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+ case 0xd0:
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+ dev_priv->card_type = NV_D0;
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+ break;
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+ default:
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+ break;
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+ }
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+ } else
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+ if ((reg0 & 0xff00fff0) == 0x20004000) {
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+ if (reg0 & 0x00f00000)
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+ dev_priv->chipset = 0x05;
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+ else
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+ dev_priv->chipset = 0x04;
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+ dev_priv->card_type = NV_04;
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+ }
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+
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+ iounmap(dev_priv->mmio);
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+ }
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+
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+ if (!dev_priv->card_type) {
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+ NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0);
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+ ret = -EINVAL;
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+ goto err_priv;
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+ }
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+
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+ NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
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+ dev_priv->card_type, reg0);
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/* map the mmio regs */
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mmio_start_offs = pci_resource_start(dev->pdev, 0);
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@@ -1029,62 +1084,6 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
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NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
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(unsigned long long)mmio_start_offs);
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-#ifdef __BIG_ENDIAN
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- /* Put the card in BE mode if it's not */
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- if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
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- nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
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-
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- DRM_MEMORYBARRIER();
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-#endif
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-
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- /* Time to determine the card architecture */
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- reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
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-
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- /* We're dealing with >=NV10 */
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- if ((reg0 & 0x0f000000) > 0) {
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- /* Bit 27-20 contain the architecture in hex */
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- dev_priv->chipset = (reg0 & 0xff00000) >> 20;
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- /* NV04 or NV05 */
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- } else if ((reg0 & 0xff00fff0) == 0x20004000) {
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- if (reg0 & 0x00f00000)
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- dev_priv->chipset = 0x05;
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- else
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- dev_priv->chipset = 0x04;
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- } else
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- dev_priv->chipset = 0xff;
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-
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- switch (dev_priv->chipset & 0xf0) {
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- case 0x00:
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- case 0x10:
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- case 0x20:
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- case 0x30:
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- dev_priv->card_type = dev_priv->chipset & 0xf0;
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- break;
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- case 0x40:
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- case 0x60:
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- dev_priv->card_type = NV_40;
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- break;
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- case 0x50:
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- case 0x80:
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- case 0x90:
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- case 0xa0:
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- dev_priv->card_type = NV_50;
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- break;
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- case 0xc0:
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- dev_priv->card_type = NV_C0;
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- break;
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- case 0xd0:
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- dev_priv->card_type = NV_D0;
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- break;
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- default:
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- NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
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- ret = -EINVAL;
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- goto err_mmio;
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- }
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-
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- NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
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- dev_priv->card_type, reg0);
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-
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/* determine frequency of timing crystal */
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strap = nv_rd32(dev, 0x101000);
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if ( dev_priv->chipset < 0x17 ||
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