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@@ -290,7 +290,7 @@ s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
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s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw,
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struct ixgbe_dcb_config *dcb_config)
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{
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- u32 i, reg;
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+ u32 i, reg, rx_pba_size;
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/* If PFC is disabled globally then fall back to LFC. */
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if (!dcb_config->pfc_mode_enable) {
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@@ -301,17 +301,23 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw,
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/* Configure PFC Tx thresholds per TC */
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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- /* Config and remember Tx */
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+ if (dcb_config->rx_pba_cfg == pba_equal)
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+ rx_pba_size = IXGBE_RXPBSIZE_64KB;
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+ else
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+ rx_pba_size = (i < 4) ? IXGBE_RXPBSIZE_80KB
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+ : IXGBE_RXPBSIZE_48KB;
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+
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+ reg = ((rx_pba_size >> 5) & 0xFFE0);
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if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full ||
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- dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx) {
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- reg = hw->fc.high_water | IXGBE_FCRTH_FCEN;
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- IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
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- reg = hw->fc.low_water | IXGBE_FCRTL_XONE;
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- IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg);
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- } else {
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- IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0);
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- IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
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- }
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+ dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx)
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+ reg |= IXGBE_FCRTL_XONE;
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+ IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg);
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+
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+ reg = ((rx_pba_size >> 2) & 0xFFE0);
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+ if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full ||
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+ dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx)
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+ reg |= IXGBE_FCRTH_FCEN;
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+ IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
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}
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/* Configure pause time (2 TCs per register) */
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