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@@ -4943,7 +4943,7 @@ static void bnx2x_init_def_sb(struct bnx2x *bp)
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int igu_seg_id;
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int port = BP_PORT(bp);
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int func = BP_FUNC(bp);
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- int reg_offset;
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+ int reg_offset, reg_offset_en5;
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u64 section;
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int index;
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struct hc_sp_status_block_data sp_sb_data;
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@@ -4966,6 +4966,8 @@ static void bnx2x_init_def_sb(struct bnx2x *bp)
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reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
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MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
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+ reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
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+ MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
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for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
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int sindex;
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/* take care of sig[0]..sig[4] */
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@@ -4980,7 +4982,7 @@ static void bnx2x_init_def_sb(struct bnx2x *bp)
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* and not 16 between the different groups
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*/
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bp->attn_group[index].sig[4] = REG_RD(bp,
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- reg_offset + 0x10 + 0x4*index);
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+ reg_offset_en5 + 0x4*index);
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else
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bp->attn_group[index].sig[4] = 0;
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}
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@@ -7625,8 +7627,11 @@ u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
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u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
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u8 *mac_addr = bp->dev->dev_addr;
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u32 val;
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+ u16 pmc;
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+
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/* The mac address is written to entries 1-4 to
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- preserve entry 0 which is used by the PMF */
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+ * preserve entry 0 which is used by the PMF
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+ */
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u8 entry = (BP_VN(bp) + 1)*8;
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val = (mac_addr[0] << 8) | mac_addr[1];
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@@ -7636,6 +7641,11 @@ u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
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(mac_addr[4] << 8) | mac_addr[5];
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EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
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+ /* Enable the PME and clear the status */
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+ pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
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+ pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
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+ pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
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+
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reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
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} else
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