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@@ -29,7 +29,7 @@
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#include <asm/hardware.h>
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-#include "generic.h"
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+#include "clock.h"
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/*
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@@ -38,23 +38,15 @@
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* PLLB be used at other rates (on boards that don't need USB), etc.
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*/
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-struct clk {
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- const char *name; /* unique clock name */
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- const char *function; /* function of the clock */
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- struct device *dev; /* device associated with function */
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- unsigned long rate_hz;
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- struct clk *parent;
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- u32 pmc_mask;
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- void (*mode)(struct clk *, int);
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- unsigned id:2; /* PCK0..3, or 32k/main/a/b */
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- unsigned primary:1;
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- unsigned pll:1;
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- unsigned programmable:1;
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- u16 users;
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-};
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+#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
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+#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
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+#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
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+
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+
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+static LIST_HEAD(clocks);
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+static DEFINE_SPINLOCK(clk_lock);
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-static spinlock_t clk_lock;
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-static u32 at91_pllb_usb_init;
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+static u32 at91_pllb_usb_init;
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/*
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* Four primary clock sources: two crystal oscillators (32K, main), and
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@@ -67,21 +59,20 @@ static struct clk clk32k = {
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.rate_hz = AT91_SLOW_CLOCK,
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.users = 1, /* always on */
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.id = 0,
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- .primary = 1,
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+ .type = CLK_TYPE_PRIMARY,
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};
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static struct clk main_clk = {
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.name = "main",
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.pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */
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.id = 1,
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- .primary = 1,
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+ .type = CLK_TYPE_PRIMARY,
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};
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static struct clk plla = {
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.name = "plla",
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.parent = &main_clk,
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.pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */
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.id = 2,
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- .primary = 1,
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- .pll = 1,
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+ .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
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};
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static void pllb_mode(struct clk *clk, int is_on)
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@@ -94,6 +85,7 @@ static void pllb_mode(struct clk *clk, int is_on)
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} else
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value = 0;
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+ // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
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at91_sys_write(AT91_CKGR_PLLBR, value);
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do {
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@@ -107,8 +99,7 @@ static struct clk pllb = {
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.pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */
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.mode = pllb_mode,
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.id = 3,
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- .primary = 1,
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- .pll = 1,
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+ .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
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};
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static void pmc_sys_mode(struct clk *clk, int is_on)
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@@ -133,41 +124,6 @@ static struct clk uhpck = {
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.mode = pmc_sys_mode,
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};
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-#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
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-/*
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- * The four programmable clocks can be parented by any primary clock.
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- * You must configure pin multiplexing to bring these signals out.
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- */
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-static struct clk pck0 = {
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- .name = "pck0",
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- .pmc_mask = AT91_PMC_PCK0,
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- .mode = pmc_sys_mode,
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- .programmable = 1,
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- .id = 0,
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-};
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-static struct clk pck1 = {
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- .name = "pck1",
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- .pmc_mask = AT91_PMC_PCK1,
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- .mode = pmc_sys_mode,
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- .programmable = 1,
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- .id = 1,
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-};
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-static struct clk pck2 = {
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- .name = "pck2",
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- .pmc_mask = AT91_PMC_PCK2,
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- .mode = pmc_sys_mode,
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- .programmable = 1,
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- .id = 2,
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-};
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-static struct clk pck3 = {
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- .name = "pck3",
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- .pmc_mask = AT91_PMC_PCK3,
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- .mode = pmc_sys_mode,
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- .programmable = 1,
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- .id = 3,
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-};
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-#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
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-
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/*
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* The master clock is divided from the CPU clock (by 1-4). It's used for
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@@ -187,131 +143,21 @@ static void pmc_periph_mode(struct clk *clk, int is_on)
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at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
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}
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-static struct clk udc_clk = {
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- .name = "udc_clk",
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- .parent = &mck,
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- .pmc_mask = 1 << AT91RM9200_ID_UDP,
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- .mode = pmc_periph_mode,
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-};
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-static struct clk ohci_clk = {
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- .name = "ohci_clk",
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- .parent = &mck,
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- .pmc_mask = 1 << AT91RM9200_ID_UHP,
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- .mode = pmc_periph_mode,
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-};
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-static struct clk ether_clk = {
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- .name = "ether_clk",
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- .parent = &mck,
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- .pmc_mask = 1 << AT91RM9200_ID_EMAC,
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- .mode = pmc_periph_mode,
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-};
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-static struct clk mmc_clk = {
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- .name = "mci_clk",
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- .parent = &mck,
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- .pmc_mask = 1 << AT91RM9200_ID_MCI,
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- .mode = pmc_periph_mode,
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-};
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-static struct clk twi_clk = {
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- .name = "twi_clk",
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- .parent = &mck,
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- .pmc_mask = 1 << AT91RM9200_ID_TWI,
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- .mode = pmc_periph_mode,
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-};
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-static struct clk usart0_clk = {
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- .name = "usart0_clk",
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- .parent = &mck,
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- .pmc_mask = 1 << AT91RM9200_ID_US0,
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- .mode = pmc_periph_mode,
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-};
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-static struct clk usart1_clk = {
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- .name = "usart1_clk",
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- .parent = &mck,
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- .pmc_mask = 1 << AT91RM9200_ID_US1,
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- .mode = pmc_periph_mode,
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-};
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-static struct clk usart2_clk = {
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- .name = "usart2_clk",
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- .parent = &mck,
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- .pmc_mask = 1 << AT91RM9200_ID_US2,
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- .mode = pmc_periph_mode,
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-};
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-static struct clk usart3_clk = {
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- .name = "usart3_clk",
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- .parent = &mck,
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- .pmc_mask = 1 << AT91RM9200_ID_US3,
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- .mode = pmc_periph_mode,
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-};
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-static struct clk spi_clk = {
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- .name = "spi0_clk",
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- .parent = &mck,
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- .pmc_mask = 1 << AT91RM9200_ID_SPI,
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- .mode = pmc_periph_mode,
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-};
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-static struct clk pioA_clk = {
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- .name = "pioA_clk",
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- .parent = &mck,
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- .pmc_mask = 1 << AT91RM9200_ID_PIOA,
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- .mode = pmc_periph_mode,
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-};
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-static struct clk pioB_clk = {
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- .name = "pioB_clk",
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- .parent = &mck,
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- .pmc_mask = 1 << AT91RM9200_ID_PIOB,
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- .mode = pmc_periph_mode,
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-};
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-static struct clk pioC_clk = {
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- .name = "pioC_clk",
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- .parent = &mck,
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- .pmc_mask = 1 << AT91RM9200_ID_PIOC,
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- .mode = pmc_periph_mode,
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-};
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-static struct clk pioD_clk = {
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- .name = "pioD_clk",
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- .parent = &mck,
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- .pmc_mask = 1 << AT91RM9200_ID_PIOD,
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- .mode = pmc_periph_mode,
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-};
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-
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-static struct clk *const clock_list[] = {
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- /* four primary clocks -- MUST BE FIRST! */
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- &clk32k,
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- &main_clk,
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- &plla,
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- &pllb,
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-
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- /* PLLB children (USB) */
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- &udpck,
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- &uhpck,
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-
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-#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
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- /* programmable clocks */
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- &pck0,
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- &pck1,
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- &pck2,
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- &pck3,
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-#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
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-
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- /* MCK and peripherals */
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- &mck,
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- &usart0_clk,
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- &usart1_clk,
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- &usart2_clk,
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- &usart3_clk,
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- &mmc_clk,
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- &udc_clk,
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- &twi_clk,
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- &spi_clk,
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- &pioA_clk,
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- &pioB_clk,
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- &pioC_clk,
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- &pioD_clk,
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- // ssc0..ssc2
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- // tc0..tc5
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- // irq0..irq6
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- &ohci_clk,
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- ðer_clk,
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-};
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+static struct clk __init *at91_css_to_clk(unsigned long css)
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+{
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+ switch (css) {
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+ case AT91_PMC_CSS_SLOW:
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+ return &clk32k;
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+ case AT91_PMC_CSS_MAIN:
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+ return &main_clk;
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+ case AT91_PMC_CSS_PLLA:
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+ return &plla;
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+ case AT91_PMC_CSS_PLLB:
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+ return &pllb;
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+ }
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+ return NULL;
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+}
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/*
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* Associate a particular clock with a function (eg, "uart") and device.
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@@ -329,14 +175,12 @@ void __init at91_clock_associate(const char *id, struct device *dev, const char
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clk->dev = dev;
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}
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-/* clocks are all static for now; no refcounting necessary */
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+/* clocks cannot be de-registered no refcounting necessary */
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struct clk *clk_get(struct device *dev, const char *id)
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{
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- int i;
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-
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- for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
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- struct clk *clk = clock_list[i];
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+ struct clk *clk;
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+ list_for_each_entry(clk, &clocks, node) {
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if (strcmp(id, clk->name) == 0)
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return clk;
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if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0)
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@@ -424,7 +268,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
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unsigned prescale;
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unsigned long actual;
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- if (!clk->programmable)
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+ if (!clk_is_programmable(clk))
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return -EINVAL;
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spin_lock_irqsave(&clk_lock, flags);
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@@ -446,7 +290,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
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unsigned prescale;
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unsigned long actual;
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- if (!clk->programmable)
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+ if (!clk_is_programmable(clk))
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return -EINVAL;
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if (clk->users)
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return -EBUSY;
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@@ -484,7 +328,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
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if (clk->users)
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return -EBUSY;
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- if (!parent->primary || !clk->programmable)
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+ if (!clk_is_primary(parent) || !clk_is_programmable(clk))
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return -EINVAL;
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spin_lock_irqsave(&clk_lock, flags);
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@@ -497,6 +341,18 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
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}
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EXPORT_SYMBOL(clk_set_parent);
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+/* establish PCK0..PCK3 parentage and rate */
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+static void init_programmable_clock(struct clk *clk)
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+{
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+ struct clk *parent;
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+ u32 pckr;
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+
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+ pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
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+ parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
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+ clk->parent = parent;
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+ clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3));
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+}
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+
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#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
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/*------------------------------------------------------------------------*/
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@@ -506,6 +362,7 @@ EXPORT_SYMBOL(clk_set_parent);
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static int at91_clk_show(struct seq_file *s, void *unused)
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{
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u32 scsr, pcsr, sr;
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+ struct clk *clk;
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unsigned i;
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seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
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@@ -523,9 +380,8 @@ static int at91_clk_show(struct seq_file *s, void *unused)
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seq_printf(s, "\n");
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- for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
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- char *state;
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- struct clk *clk = clock_list[i];
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+ list_for_each_entry(clk, &clocks, node) {
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+ char *state;
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if (clk->mode == pmc_sys_mode)
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state = (scsr & clk->pmc_mask) ? "on" : "off";
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@@ -568,6 +424,28 @@ postcore_initcall(at91_clk_debugfs_init);
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#endif
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+/*------------------------------------------------------------------------*/
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+
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+/* Register a new clock */
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+int __init clk_register(struct clk *clk)
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+{
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+ if (clk_is_peripheral(clk)) {
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+ clk->parent = &mck;
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+ clk->mode = pmc_periph_mode;
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+ list_add_tail(&clk->node, &clocks);
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+ }
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+#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
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+ else if (clk_is_programmable(clk)) {
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+ clk->mode = pmc_sys_mode;
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+ init_programmable_clock(clk);
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+ list_add_tail(&clk->node, &clocks);
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+ }
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+#endif
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+
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+ return 0;
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+}
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+
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+
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/*------------------------------------------------------------------------*/
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static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
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@@ -640,20 +518,17 @@ fail:
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return 0;
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}
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-
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/*
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* Several unused clocks may be active. Turn them off.
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*/
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-static void at91_periphclk_reset(void)
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+static void __init at91_periphclk_reset(void)
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{
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unsigned long reg;
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- int i;
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+ struct clk *clk;
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reg = at91_sys_read(AT91_PMC_PCSR);
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- for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
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- struct clk *clk = clock_list[i];
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-
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+ list_for_each_entry(clk, &clocks, node) {
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if (clk->mode != pmc_periph_mode)
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continue;
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@@ -664,11 +539,25 @@ static void at91_periphclk_reset(void)
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at91_sys_write(AT91_PMC_PCDR, reg);
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}
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+static struct clk *const standard_pmc_clocks[] __initdata = {
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+ /* four primary clocks */
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+ &clk32k,
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+ &main_clk,
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+ &plla,
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+ &pllb,
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+
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+ /* PLLB children (USB) */
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+ &udpck,
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+ &uhpck,
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+
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+ /* MCK */
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+ &mck
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+};
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+
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int __init at91_clock_init(unsigned long main_clock)
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{
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unsigned tmp, freq, mckr;
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-
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- spin_lock_init(&clk_lock);
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+ int i;
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/*
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* When the bootloader initialized the main oscillator correctly,
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@@ -709,11 +598,15 @@ int __init at91_clock_init(unsigned long main_clock)
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* For now, assume this parentage won't change.
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*/
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mckr = at91_sys_read(AT91_PMC_MCKR);
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- mck.parent = clock_list[mckr & AT91_PMC_CSS];
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+ mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
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freq = mck.parent->rate_hz;
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freq /= (1 << ((mckr >> 2) & 3)); /* prescale */
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mck.rate_hz = freq / (1 + ((mckr >> 8) & 3)); /* mdiv */
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+ /* Register the PMC's standard clocks */
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+ for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
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+ list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
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+
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/* MCK and CPU clock are "always on" */
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clk_enable(&mck);
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@@ -722,35 +615,8 @@ int __init at91_clock_init(unsigned long main_clock)
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(unsigned) main_clock / 1000000,
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((unsigned) main_clock % 1000000) / 1000);
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-#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
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- /* establish PCK0..PCK3 parentage */
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- for (tmp = 0; tmp < ARRAY_SIZE(clock_list); tmp++) {
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- struct clk *clk = clock_list[tmp], *parent;
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- u32 pckr;
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-
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- if (!clk->programmable)
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- continue;
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-
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- pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
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- parent = clock_list[pckr & AT91_PMC_CSS];
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- clk->parent = parent;
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- clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3));
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-
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- if (clk->users == 0) {
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- /* not being used, so switch it off */
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- at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
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- }
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- }
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-#else
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/* disable all programmable clocks */
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at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK0 | AT91_PMC_PCK1 | AT91_PMC_PCK2 | AT91_PMC_PCK3);
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-#endif
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-
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- /* enable the PIO clocks */
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- clk_enable(&pioA_clk);
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- clk_enable(&pioB_clk);
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- clk_enable(&pioC_clk);
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- clk_enable(&pioD_clk);
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/* disable all other unused peripheral clocks */
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at91_periphclk_reset();
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Andrew Victor