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@@ -1389,6 +1389,71 @@ static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
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rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
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}
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+static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
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+ void __iomem *ioaddr)
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+{
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+ struct pci_dev *pdev = tp->pci_dev;
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+ u16 vendor_id, device_id;
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+
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+ pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
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+ pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
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+
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+ if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
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+ return;
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+
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+ mdio_write(ioaddr, 0x1f, 0x0001);
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+ mdio_write(ioaddr, 0x10, 0xf01b);
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+ mdio_write(ioaddr, 0x1f, 0x0000);
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+}
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+
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+static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
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+ void __iomem *ioaddr)
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+{
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+ struct phy_reg phy_reg_init[] = {
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+ { 0x1f, 0x0001 },
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+ { 0x04, 0x0000 },
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+ { 0x03, 0x00a1 },
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+ { 0x02, 0x0008 },
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+ { 0x01, 0x0120 },
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+ { 0x00, 0x1000 },
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+ { 0x04, 0x0800 },
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+ { 0x04, 0x9000 },
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+ { 0x03, 0x802f },
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+ { 0x02, 0x4f02 },
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+ { 0x01, 0x0409 },
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+ { 0x00, 0xf099 },
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+ { 0x04, 0x9800 },
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+ { 0x04, 0xa000 },
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+ { 0x03, 0xdf01 },
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+ { 0x02, 0xdf20 },
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+ { 0x01, 0xff95 },
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+ { 0x00, 0xba00 },
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+ { 0x04, 0xa800 },
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+ { 0x04, 0xf000 },
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+ { 0x03, 0xdf01 },
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+ { 0x02, 0xdf20 },
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+ { 0x01, 0x101a },
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+ { 0x00, 0xa0ff },
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+ { 0x04, 0xf800 },
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+ { 0x04, 0x0000 },
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+ { 0x1f, 0x0000 },
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+
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+ { 0x1f, 0x0001 },
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+ { 0x10, 0xf41b },
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+ { 0x14, 0xfb54 },
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+ { 0x18, 0xf5c7 },
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+ { 0x1f, 0x0000 },
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+
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+ { 0x1f, 0x0001 },
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+ { 0x17, 0x0cc0 },
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+ { 0x1f, 0x0000 }
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+ };
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+
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+ rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
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+
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+ rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
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+}
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+
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static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
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{
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struct phy_reg phy_reg_init[] = {
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@@ -1681,6 +1746,9 @@ static void rtl_hw_phy_config(struct net_device *dev)
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case RTL_GIGA_MAC_VER_04:
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rtl8169sb_hw_phy_config(ioaddr);
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break;
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+ case RTL_GIGA_MAC_VER_05:
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+ rtl8169scd_hw_phy_config(tp, ioaddr);
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+ break;
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case RTL_GIGA_MAC_VER_06:
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rtl8169sce_hw_phy_config(ioaddr);
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break;
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