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@@ -13,17 +13,23 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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+#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/mach/irq.h>
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-#include <asm/irq.h>
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-#include <asm/io.h>
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-#define INTC_REVISION 0x0000
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-#define INTC_SYSCONFIG 0x0010
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-#define INTC_SYSSTATUS 0x0014
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-#define INTC_CONTROL 0x0048
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-#define INTC_MIR_CLEAR0 0x0088
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-#define INTC_MIR_SET0 0x008c
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+
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+/* selected INTC register offsets */
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+
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+#define INTC_REVISION 0x0000
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+#define INTC_SYSCONFIG 0x0010
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+#define INTC_SYSSTATUS 0x0014
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+#define INTC_CONTROL 0x0048
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+#define INTC_MIR_CLEAR0 0x0088
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+#define INTC_MIR_SET0 0x008c
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+#define INTC_PENDING_IRQ0 0x0098
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+
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+/* Number of IRQ state bits in each MIR register */
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+#define IRQ_BITS_PER_REG 32
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/*
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* OMAP2 has a number of different interrupt controllers, each interrupt
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@@ -42,36 +48,40 @@ static struct omap_irq_bank {
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},
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};
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+/* INTC bank register get/set */
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+
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+static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
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+{
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+ __raw_writel(val, bank->base_reg + reg);
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+}
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+
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+static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
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+{
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+ return __raw_readl(bank->base_reg + reg);
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+}
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+
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/* XXX: FIQ and additional INTC support (only MPU at the moment) */
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static void omap_ack_irq(unsigned int irq)
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{
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- __raw_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL);
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+ intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
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}
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static void omap_mask_irq(unsigned int irq)
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{
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- int offset = (irq >> 5) << 5;
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+ int offset = irq & (~(IRQ_BITS_PER_REG - 1));
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- if (irq >= 64) {
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- irq %= 64;
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- } else if (irq >= 32) {
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- irq %= 32;
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- }
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+ irq &= (IRQ_BITS_PER_REG - 1);
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- __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset);
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+ intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
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}
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static void omap_unmask_irq(unsigned int irq)
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{
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- int offset = (irq >> 5) << 5;
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+ int offset = irq & (~(IRQ_BITS_PER_REG - 1));
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- if (irq >= 64) {
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- irq %= 64;
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- } else if (irq >= 32) {
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- irq %= 32;
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- }
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+ irq &= (IRQ_BITS_PER_REG - 1);
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- __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset);
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+ intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
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}
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static void omap_mask_ack_irq(unsigned int irq)
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@@ -91,20 +101,20 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
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{
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unsigned long tmp;
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- tmp = __raw_readl(bank->base_reg + INTC_REVISION) & 0xff;
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+ tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
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printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
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"(revision %ld.%ld) with %d interrupts\n",
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bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
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- tmp = __raw_readl(bank->base_reg + INTC_SYSCONFIG);
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+ tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
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tmp |= 1 << 1; /* soft reset */
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- __raw_writel(tmp, bank->base_reg + INTC_SYSCONFIG);
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+ intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
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- while (!(__raw_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1))
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+ while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
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/* Wait for reset to complete */;
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/* Enable autoidle */
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- __raw_writel(1 << 0, bank->base_reg + INTC_SYSCONFIG);
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+ intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
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}
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void __init omap_init_irq(void)
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@@ -117,7 +127,8 @@ void __init omap_init_irq(void)
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struct omap_irq_bank *bank = irq_banks + i;
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if (cpu_is_omap24xx())
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- bank->base_reg = IO_ADDRESS(OMAP24XX_IC_BASE);
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+ bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
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+
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omap_irq_bank_init_one(bank);
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nr_irqs += bank->nr_irqs;
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