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@@ -1,9 +1,13 @@
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+/* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
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+ * Copyright (C) 2006 Kyle McMartin <kyle@parisc-linux.org>
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+ */
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+
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#ifndef _ASM_PARISC_ATOMIC_H_
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#define _ASM_PARISC_ATOMIC_H_
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#include <linux/config.h>
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+#include <linux/types.h>
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#include <asm/system.h>
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-/* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>. */
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/*
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* Atomic operations that C can't guarantee us. Useful for
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@@ -46,15 +50,6 @@ extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned;
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# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0)
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#endif
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-/* Note that we need not lock read accesses - aligned word writes/reads
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- * are atomic, so a reader never sees unconsistent values.
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- *
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- * Cache-line alignment would conflict with, for example, linux/module.h
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- */
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-
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-typedef struct { volatile int counter; } atomic_t;
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-
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-
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/* This should get optimized out since it's never called.
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** Or get a link error if xchg is used "wrong".
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*/
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@@ -69,10 +64,9 @@ extern unsigned long __xchg64(unsigned long, unsigned long *);
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#endif
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/* optimizer better get rid of switch since size is a constant */
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-static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
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- int size)
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+static __inline__ unsigned long
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+__xchg(unsigned long x, __volatile__ void * ptr, int size)
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{
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-
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switch(size) {
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#ifdef __LP64__
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case 8: return __xchg64(x,(unsigned long *) ptr);
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@@ -129,7 +123,13 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
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(unsigned long)_n_, sizeof(*(ptr))); \
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})
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+/* Note that we need not lock read accesses - aligned word writes/reads
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+ * are atomic, so a reader never sees unconsistent values.
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+ *
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+ * Cache-line alignment would conflict with, for example, linux/module.h
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+ */
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+typedef struct { volatile int counter; } atomic_t;
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/* It's possible to reduce all atomic operations to either
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* __atomic_add_return, atomic_set and atomic_read (the latter
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@@ -210,12 +210,66 @@ static __inline__ int atomic_read(const atomic_t *v)
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#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
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-#define ATOMIC_INIT(i) { (i) }
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+#define ATOMIC_INIT(i) ((atomic_t) { (i) })
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#define smp_mb__before_atomic_dec() smp_mb()
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#define smp_mb__after_atomic_dec() smp_mb()
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#define smp_mb__before_atomic_inc() smp_mb()
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#define smp_mb__after_atomic_inc() smp_mb()
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+#ifdef __LP64__
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+
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+typedef struct { volatile s64 counter; } atomic64_t;
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+
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+#define ATOMIC64_INIT(i) ((atomic64_t) { (i) })
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+
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+static __inline__ int
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+__atomic64_add_return(s64 i, atomic64_t *v)
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+{
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+ int ret;
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+ unsigned long flags;
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+ _atomic_spin_lock_irqsave(v, flags);
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+
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+ ret = (v->counter += i);
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+
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+ _atomic_spin_unlock_irqrestore(v, flags);
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+ return ret;
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+}
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+
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+static __inline__ void
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+atomic64_set(atomic64_t *v, s64 i)
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+{
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+ unsigned long flags;
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+ _atomic_spin_lock_irqsave(v, flags);
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+
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+ v->counter = i;
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+
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+ _atomic_spin_unlock_irqrestore(v, flags);
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+}
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+
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+static __inline__ s64
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+atomic64_read(const atomic64_t *v)
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+{
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+ return v->counter;
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+}
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+
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+#define atomic64_add(i,v) ((void)(__atomic64_add_return( ((s64)i),(v))))
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+#define atomic64_sub(i,v) ((void)(__atomic64_add_return(-((s64)i),(v))))
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+#define atomic64_inc(v) ((void)(__atomic64_add_return( 1,(v))))
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+#define atomic64_dec(v) ((void)(__atomic64_add_return( -1,(v))))
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+
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+#define atomic64_add_return(i,v) (__atomic64_add_return( ((s64)i),(v)))
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+#define atomic64_sub_return(i,v) (__atomic64_add_return(-((s64)i),(v)))
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+#define atomic64_inc_return(v) (__atomic64_add_return( 1,(v)))
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+#define atomic64_dec_return(v) (__atomic64_add_return( -1,(v)))
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+
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+#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
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+
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+#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
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+#define atomic64_dec_and_test(v) (atomic64_dec_return(v) == 0)
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+
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+#endif /* __LP64__ */
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+
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#include <asm-generic/atomic.h>
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-#endif
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+
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+#endif /* _ASM_PARISC_ATOMIC_H_ */
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