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@@ -2729,6 +2729,7 @@ static struct dibx000_agc_config stk7700p_7000p_xc4000_agc_config = {
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.agc2_pt2 = 0x80,
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.agc2_slope1 = 0x1d,
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.agc2_slope2 = 0x1d,
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+ .alpha_mant = 0x11,
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.alpha_exp = 0x1b,
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.beta_mant = 0x17,
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.beta_exp = 0x33,
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@@ -2738,10 +2739,10 @@ static struct dibx000_agc_config stk7700p_7000p_xc4000_agc_config = {
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/* validation:
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reg 900 (0x0384) = 0x0e60
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reg 903 (0x0387) = 0x0027
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- reg 18 (0x0012) = 0x0321
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- reg 19 (0x0013) = 0x1620
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- reg 21 (0x0015) = 0x0265
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- reg 22 (0x0016) = 0x6cbd
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+ reg 18 (0x0012) = 0x0321 (0393)
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+ reg 19 (0x0013) = 0x1620 (8700)
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+ reg 21 (0x0015) = 0x0265 (0258)
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+ reg 22 (0x0016) = 0x6cbd (bf26)
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reg 23 (0x0017) = 0x0138
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reg 24 (0x0018) = 0x1381
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reg 72 (0x0048) = 0xd257
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@@ -2766,11 +2767,11 @@ static struct dibx000_agc_config stk7700p_7000p_xc4000_agc_config = {
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xtal_hz = ? (val dependent on exact tuning freq)
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*/
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static struct dibx000_bandwidth_config stk7700p_xc4000_pll_config = {
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- 52500, 30000, // internal, sampling
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- 1, 7, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass
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+ 60000, 30000, // internal, sampling
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+ 1, 8, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass
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0, 0, 1, 1, 0, // misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc, modulo
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- (3 << 14) | (1 << 12) | (599 << 0), // sad_cfg: refsel, sel, freq_15k
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- 40201405, // ifreq
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+ (3 << 14) | (1 << 12) | (524 << 0), // sad_cfg: refsel, sel, freq_15k
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+ 39370534, // ifreq
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20452225, // timf
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30000000, // xtal
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};
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