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@@ -782,12 +782,16 @@ void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
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printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
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printk("%s", lvl);
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+
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+ /* dump buffer after the mark */
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for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
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for (word = 0; word < 8; word++)
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data[word] = htonl(REG_RD(bp, offset + 4*word));
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data[8] = 0x0;
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pr_cont("%s", (char *)data);
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}
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+
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+ /* dump buffer before the mark */
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for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
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for (word = 0; word < 8; word++)
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data[word] = htonl(REG_RD(bp, offset + 4*word));
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@@ -1683,11 +1687,11 @@ static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
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}
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/**
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- * bnx2x_trylock_leader_lock- try to aquire a leader lock.
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+ * bnx2x_trylock_leader_lock- try to acquire a leader lock.
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*
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* @bp: driver handle
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*
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- * Tries to aquire a leader lock for current engine.
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+ * Tries to acquire a leader lock for current engine.
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*/
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static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
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{
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@@ -1804,7 +1808,7 @@ void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
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* mark pending ACK to MCP bit.
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* prevent case that both bits are cleared.
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* At the end of load/unload driver checks that
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- * sp_state is cleaerd, and this order prevents
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+ * sp_state is cleared, and this order prevents
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* races
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*/
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smp_mb__before_clear_bit();
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@@ -3083,7 +3087,7 @@ static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
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/* Maximum number or simultaneous TPA aggregation for this Queue.
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*
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- * For PF Clients it should be the maximum avaliable number.
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+ * For PF Clients it should be the maximum available number.
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* VF driver(s) may want to define it to a smaller value.
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*/
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rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
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@@ -3796,7 +3800,7 @@ static void bnx2x_fan_failure(struct bnx2x *bp)
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"Please contact OEM Support for assistance\n");
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/*
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- * Scheudle device reset (unload)
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+ * Schedule device reset (unload)
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* This is due to some boards consuming sufficient power when driver is
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* up to overheat if fan fails.
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*/
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@@ -4894,7 +4898,7 @@ static void bnx2x_after_function_update(struct bnx2x *bp)
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struct bnx2x_queue_update_params *q_update_params =
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&queue_params.params.update;
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- /* Send Q update command with afex vlan removal values for all Qs */
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+ /* Send Q update command with afex vlan removal values for all Qs */
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queue_params.cmd = BNX2X_Q_CMD_UPDATE;
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/* set silent vlan removal values according to vlan mode */
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@@ -4996,7 +5000,6 @@ static void bnx2x_eq_int(struct bnx2x *bp)
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for (; sw_cons != hw_cons;
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sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
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-
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elem = &bp->eq_ring[EQ_DESC(sw_cons)];
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rc = bnx2x_iov_eq_sp_event(bp, elem);
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@@ -6480,7 +6483,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp)
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DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
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/*
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- * take the UNDI lock to protect undi_unload flow from accessing
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+ * take the RESET lock to protect undi_unload flow from accessing
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* registers while we're resetting the chip
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*/
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bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
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@@ -6610,7 +6613,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp)
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* queues with "old" ILT addresses.
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* c. PF enable in the PGLC.
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* d. Clear the was_error of the PF in the PGLC. (could have
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- * occured while driver was down)
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+ * occurred while driver was down)
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* e. PF enable in the CFC (WEAK + STRONG)
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* f. Timers scan enable
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* 3. PF driver unload flow:
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@@ -6651,7 +6654,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp)
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/* Step 1: set zeroes to all ilt page entries with valid bit on
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* Step 2: set the timers first/last ilt entry to point
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* to the entire range to prevent ILT range error for 3rd/4th
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- * vnic (this code assumes existance of the vnic)
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+ * vnic (this code assumes existence of the vnic)
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*
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* both steps performed by call to bnx2x_ilt_client_init_op()
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* with dummy TM client
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@@ -6668,7 +6671,6 @@ static int bnx2x_init_hw_common(struct bnx2x *bp)
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REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
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}
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-
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REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
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REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
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@@ -7151,7 +7153,6 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
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}
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}
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-
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/* If SPIO5 is set to generate interrupts, enable it for this port */
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val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
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if (val & MISC_SPIO_SPIO5) {
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@@ -8335,8 +8336,8 @@ static void bnx2x_reset_func(struct bnx2x *bp)
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/* SP SB */
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REG_WR8(bp, BAR_CSTRORM_INTMEM +
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- CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
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- SB_DISABLED);
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+ CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
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+ SB_DISABLED);
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for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
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REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
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@@ -9078,8 +9079,7 @@ static int bnx2x_process_kill(struct bnx2x *bp, bool global)
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int cnt = 1000;
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u32 val = 0;
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u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
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- u32 tags_63_32 = 0;
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-
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+ u32 tags_63_32 = 0;
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/* Empty the Tetris buffer, wait for 1s */
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do {
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@@ -9974,7 +9974,6 @@ static int bnx2x_prev_unload(struct bnx2x *bp)
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REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
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}
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-
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do {
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/* Lock MCP using an unload request */
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fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
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@@ -10694,21 +10693,21 @@ static void bnx2x_get_fcoe_info(struct bnx2x *bp)
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/* Port info */
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bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
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SHMEM_RD(bp,
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- dev_info.port_hw_config[port].
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+ dev_info.port_hw_config[port].
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fcoe_wwn_port_name_upper);
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bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
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SHMEM_RD(bp,
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- dev_info.port_hw_config[port].
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+ dev_info.port_hw_config[port].
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fcoe_wwn_port_name_lower);
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/* Node info */
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bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
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SHMEM_RD(bp,
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- dev_info.port_hw_config[port].
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+ dev_info.port_hw_config[port].
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fcoe_wwn_node_name_upper);
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bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
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SHMEM_RD(bp,
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- dev_info.port_hw_config[port].
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+ dev_info.port_hw_config[port].
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fcoe_wwn_node_name_lower);
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} else if (!IS_MF_SD(bp)) {
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/*
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@@ -11611,7 +11610,6 @@ static int bnx2x_set_mc_list(struct bnx2x *bp)
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return rc;
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}
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-
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/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
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void bnx2x_set_rx_mode(struct net_device *dev)
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{
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@@ -11899,13 +11897,14 @@ static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
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* support Physical Device Assignment where kernel BDF maybe arbitrary
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* (depending on hypervisor).
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*/
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- if (chip_is_e1x)
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+ if (chip_is_e1x) {
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bp->pf_num = PCI_FUNC(pdev->devfn);
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- else {/* chip is E2/3*/
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+ } else {
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+ /* chip is E2/3*/
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pci_read_config_dword(bp->pdev,
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PCICFG_ME_REGISTER, &pci_cfg_dword);
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bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
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- ME_REG_ABS_PF_NUM_SHIFT);
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+ ME_REG_ABS_PF_NUM_SHIFT);
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}
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BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
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@@ -12426,7 +12425,7 @@ static int bnx2x_init_one(struct pci_dev *pdev,
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BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
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BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
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BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
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- tx_count, rx_count);
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+ tx_count, rx_count);
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rc = bnx2x_init_bp(bp);
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if (rc)
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Yuval Mintz