|
@@ -7,7 +7,7 @@ config ARM
|
|
|
select HAVE_MEMBLOCK
|
|
|
select RTC_LIB
|
|
|
select SYS_SUPPORTS_APM_EMULATION
|
|
|
- select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
|
|
|
+ select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
|
|
|
select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
|
|
|
select HAVE_ARCH_KGDB
|
|
|
select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
|
|
@@ -24,7 +24,7 @@ config ARM
|
|
|
select HAVE_PERF_EVENTS
|
|
|
select PERF_USE_VMALLOC
|
|
|
select HAVE_REGS_AND_STACK_ACCESS_API
|
|
|
- select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
|
|
|
+ select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
|
|
|
select HAVE_C_RECORDMCOUNT
|
|
|
select HAVE_GENERIC_HARDIRQS
|
|
|
select HAVE_SPARSE_IRQ
|
|
@@ -63,6 +63,10 @@ config GENERIC_CLOCKEVENTS_BROADCAST
|
|
|
depends on GENERIC_CLOCKEVENTS
|
|
|
default y if SMP
|
|
|
|
|
|
+config KTIME_SCALAR
|
|
|
+ bool
|
|
|
+ default y
|
|
|
+
|
|
|
config HAVE_TCM
|
|
|
bool
|
|
|
select GENERIC_ALLOCATOR
|
|
@@ -178,11 +182,6 @@ config FIQ
|
|
|
config ARCH_MTD_XIP
|
|
|
bool
|
|
|
|
|
|
-config ARM_L1_CACHE_SHIFT_6
|
|
|
- bool
|
|
|
- help
|
|
|
- Setting ARM L1 cache line size to 64 Bytes.
|
|
|
-
|
|
|
config VECTORS_BASE
|
|
|
hex
|
|
|
default 0xffff0000 if MMU || CPU_HIGH_VECTOR
|
|
@@ -191,6 +190,22 @@ config VECTORS_BASE
|
|
|
help
|
|
|
The base address of exception vectors.
|
|
|
|
|
|
+config ARM_PATCH_PHYS_VIRT
|
|
|
+ bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
|
|
|
+ depends on EXPERIMENTAL
|
|
|
+ depends on !XIP_KERNEL && MMU
|
|
|
+ depends on !ARCH_REALVIEW || !SPARSEMEM
|
|
|
+ help
|
|
|
+ Patch phys-to-virt translation functions at runtime according to
|
|
|
+ the position of the kernel in system memory.
|
|
|
+
|
|
|
+ This can only be used with non-XIP with MMU kernels where
|
|
|
+ the base of physical memory is at a 16MB boundary.
|
|
|
+
|
|
|
+config ARM_PATCH_PHYS_VIRT_16BIT
|
|
|
+ def_bool y
|
|
|
+ depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
|
|
|
+
|
|
|
source "init/Kconfig"
|
|
|
|
|
|
source "kernel/Kconfig.freezer"
|
|
@@ -212,15 +227,6 @@ choice
|
|
|
prompt "ARM system type"
|
|
|
default ARCH_VERSATILE
|
|
|
|
|
|
-config ARCH_AAEC2000
|
|
|
- bool "Agilent AAEC-2000 based"
|
|
|
- select CPU_ARM920T
|
|
|
- select ARM_AMBA
|
|
|
- select HAVE_CLK
|
|
|
- select ARCH_USES_GETTIMEOFFSET
|
|
|
- help
|
|
|
- This enables support for systems based on the Agilent AAEC-2000
|
|
|
-
|
|
|
config ARCH_INTEGRATOR
|
|
|
bool "ARM Ltd. Integrator family"
|
|
|
select ARM_AMBA
|
|
@@ -346,7 +352,7 @@ config ARCH_FOOTBRIDGE
|
|
|
bool "FootBridge"
|
|
|
select CPU_SA110
|
|
|
select FOOTBRIDGE
|
|
|
- select ARCH_USES_GETTIMEOFFSET
|
|
|
+ select GENERIC_CLOCKEVENTS
|
|
|
help
|
|
|
Support for systems based on the DC21285 companion chip
|
|
|
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
|
|
@@ -457,6 +463,7 @@ config ARCH_IXP4XX
|
|
|
|
|
|
config ARCH_DOVE
|
|
|
bool "Marvell Dove"
|
|
|
+ select CPU_V6K
|
|
|
select PCI
|
|
|
select ARCH_REQUIRE_GPIOLIB
|
|
|
select GENERIC_CLOCKEVENTS
|
|
@@ -795,17 +802,6 @@ config ARCH_TCC_926
|
|
|
help
|
|
|
Support for Telechips TCC ARM926-based systems.
|
|
|
|
|
|
-config ARCH_LH7A40X
|
|
|
- bool "Sharp LH7A40X"
|
|
|
- select CPU_ARM922T
|
|
|
- select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
|
|
|
- select ARCH_USES_GETTIMEOFFSET
|
|
|
- help
|
|
|
- Say Y here for systems based on one of the Sharp LH7A40X
|
|
|
- System on a Chip processors. These CPUs include an ARM922T
|
|
|
- core with a wide array of integrated devices for
|
|
|
- hand-held and low-power applications.
|
|
|
-
|
|
|
config ARCH_U300
|
|
|
bool "ST-Ericsson U300 Series"
|
|
|
depends on MMU
|
|
@@ -875,6 +871,16 @@ config PLAT_SPEAR
|
|
|
help
|
|
|
Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
|
|
|
|
|
|
+config ARCH_VT8500
|
|
|
+ bool "VIA/WonderMedia 85xx"
|
|
|
+ select CPU_ARM926T
|
|
|
+ select GENERIC_GPIO
|
|
|
+ select ARCH_HAS_CPUFREQ
|
|
|
+ select GENERIC_CLOCKEVENTS
|
|
|
+ select ARCH_REQUIRE_GPIOLIB
|
|
|
+ select HAVE_PWM
|
|
|
+ help
|
|
|
+ Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
|
|
|
endchoice
|
|
|
|
|
|
#
|
|
@@ -882,8 +888,6 @@ endchoice
|
|
|
# Kconfigs may be included either alphabetically (according to the
|
|
|
# plat- suffix) or along side the corresponding mach-* source.
|
|
|
#
|
|
|
-source "arch/arm/mach-aaec2000/Kconfig"
|
|
|
-
|
|
|
source "arch/arm/mach-at91/Kconfig"
|
|
|
|
|
|
source "arch/arm/mach-bcmring/Kconfig"
|
|
@@ -922,8 +926,6 @@ source "arch/arm/mach-kirkwood/Kconfig"
|
|
|
|
|
|
source "arch/arm/mach-ks8695/Kconfig"
|
|
|
|
|
|
-source "arch/arm/mach-lh7a40x/Kconfig"
|
|
|
-
|
|
|
source "arch/arm/mach-loki/Kconfig"
|
|
|
|
|
|
source "arch/arm/mach-lpc32xx/Kconfig"
|
|
@@ -1007,6 +1009,8 @@ source "arch/arm/mach-versatile/Kconfig"
|
|
|
|
|
|
source "arch/arm/mach-vexpress/Kconfig"
|
|
|
|
|
|
+source "arch/arm/mach-vt8500/Kconfig"
|
|
|
+
|
|
|
source "arch/arm/mach-w90x900/Kconfig"
|
|
|
|
|
|
# Definitions to make life easier
|
|
@@ -1048,7 +1052,7 @@ config XSCALE_PMU
|
|
|
default y
|
|
|
|
|
|
config CPU_HAS_PMU
|
|
|
- depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \
|
|
|
+ depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
|
|
|
(!ARCH_OMAP3 || OMAP3_EMU)
|
|
|
default y
|
|
|
bool
|
|
@@ -1064,7 +1068,7 @@ endif
|
|
|
|
|
|
config ARM_ERRATA_411920
|
|
|
bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
|
|
|
- depends on CPU_V6
|
|
|
+ depends on CPU_V6 || CPU_V6K
|
|
|
help
|
|
|
Invalidation of the Instruction Cache operation can
|
|
|
fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
|
|
@@ -1140,7 +1144,7 @@ config ARM_ERRATA_742231
|
|
|
|
|
|
config PL310_ERRATA_588369
|
|
|
bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
|
|
|
- depends on CACHE_L2X0 && ARCH_OMAP4
|
|
|
+ depends on CACHE_L2X0
|
|
|
help
|
|
|
The PL310 L2 cache controller implements three types of Clean &
|
|
|
Invalidate maintenance operations: by Physical Address
|
|
@@ -1149,8 +1153,7 @@ config PL310_ERRATA_588369
|
|
|
clean operation followed immediately by an invalidate operation,
|
|
|
both performing to the same memory location. This functionality
|
|
|
is not correctly implemented in PL310 as clean lines are not
|
|
|
- invalidated as a result of these operations. Note that this errata
|
|
|
- uses Texas Instrument's secure monitor api.
|
|
|
+ invalidated as a result of these operations.
|
|
|
|
|
|
config ARM_ERRATA_720789
|
|
|
bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
|
|
@@ -1164,6 +1167,17 @@ config ARM_ERRATA_720789
|
|
|
tables. The workaround changes the TLB flushing routines to invalidate
|
|
|
entries regardless of the ASID.
|
|
|
|
|
|
+config PL310_ERRATA_727915
|
|
|
+ bool "Background Clean & Invalidate by Way operation can cause data corruption"
|
|
|
+ depends on CACHE_L2X0
|
|
|
+ help
|
|
|
+ PL310 implements the Clean & Invalidate by Way L2 cache maintenance
|
|
|
+ operation (offset 0x7FC). This operation runs in background so that
|
|
|
+ PL310 can handle normal accesses while it is in progress. Under very
|
|
|
+ rare circumstances, due to this erratum, write data can be lost when
|
|
|
+ PL310 treats a cacheable write transaction during a Clean &
|
|
|
+ Invalidate by Way operation.
|
|
|
+
|
|
|
config ARM_ERRATA_743622
|
|
|
bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
|
|
|
depends on CPU_V7
|
|
@@ -1202,6 +1216,28 @@ config ARM_ERRATA_753970
|
|
|
This has the same effect as the cache sync operation: store buffer
|
|
|
drain and waiting for all buffers empty.
|
|
|
|
|
|
+config ARM_ERRATA_754322
|
|
|
+ bool "ARM errata: possible faulty MMU translations following an ASID switch"
|
|
|
+ depends on CPU_V7
|
|
|
+ help
|
|
|
+ This option enables the workaround for the 754322 Cortex-A9 (r2p*,
|
|
|
+ r3p*) erratum. A speculative memory access may cause a page table walk
|
|
|
+ which starts prior to an ASID switch but completes afterwards. This
|
|
|
+ can populate the micro-TLB with a stale entry which may be hit with
|
|
|
+ the new ASID. This workaround places two dsb instructions in the mm
|
|
|
+ switching code so that no page table walks can cross the ASID switch.
|
|
|
+
|
|
|
+config ARM_ERRATA_754327
|
|
|
+ bool "ARM errata: no automatic Store Buffer drain"
|
|
|
+ depends on CPU_V7 && SMP
|
|
|
+ help
|
|
|
+ This option enables the workaround for the 754327 Cortex-A9 (prior to
|
|
|
+ r2p0) erratum. The Store Buffer does not have any automatic draining
|
|
|
+ mechanism and therefore a livelock may occur if an external agent
|
|
|
+ continuously polls a memory location waiting to observe an update.
|
|
|
+ This workaround defines cpu_relax() as smp_mb(), preventing correctly
|
|
|
+ written polling loops from denying visibility of updates to memory.
|
|
|
+
|
|
|
endmenu
|
|
|
|
|
|
source "arch/arm/common/Kconfig"
|
|
@@ -1275,6 +1311,7 @@ source "kernel/time/Kconfig"
|
|
|
config SMP
|
|
|
bool "Symmetric Multi-Processing (EXPERIMENTAL)"
|
|
|
depends on EXPERIMENTAL
|
|
|
+ depends on CPU_V6K || CPU_V7
|
|
|
depends on GENERIC_CLOCKEVENTS
|
|
|
depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
|
|
|
MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
|
|
@@ -1386,7 +1423,7 @@ config HZ
|
|
|
|
|
|
config THUMB2_KERNEL
|
|
|
bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
|
|
|
- depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL
|
|
|
+ depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
|
|
|
select AEABI
|
|
|
select ARM_ASM_UNIFIED
|
|
|
help
|
|
@@ -1396,6 +1433,37 @@ config THUMB2_KERNEL
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
+config THUMB2_AVOID_R_ARM_THM_JUMP11
|
|
|
+ bool "Work around buggy Thumb-2 short branch relocations in gas"
|
|
|
+ depends on THUMB2_KERNEL && MODULES
|
|
|
+ default y
|
|
|
+ help
|
|
|
+ Various binutils versions can resolve Thumb-2 branches to
|
|
|
+ locally-defined, preemptible global symbols as short-range "b.n"
|
|
|
+ branch instructions.
|
|
|
+
|
|
|
+ This is a problem, because there's no guarantee the final
|
|
|
+ destination of the symbol, or any candidate locations for a
|
|
|
+ trampoline, are within range of the branch. For this reason, the
|
|
|
+ kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
|
|
|
+ relocation in modules at all, and it makes little sense to add
|
|
|
+ support.
|
|
|
+
|
|
|
+ The symptom is that the kernel fails with an "unsupported
|
|
|
+ relocation" error when loading some modules.
|
|
|
+
|
|
|
+ Until fixed tools are available, passing
|
|
|
+ -fno-optimize-sibling-calls to gcc should prevent gcc generating
|
|
|
+ code which hits this problem, at the cost of a bit of extra runtime
|
|
|
+ stack usage in some cases.
|
|
|
+
|
|
|
+ The problem is described in more detail at:
|
|
|
+ https://bugs.launchpad.net/binutils-linaro/+bug/725126
|
|
|
+
|
|
|
+ Only Thumb-2 kernels are affected.
|
|
|
+
|
|
|
+ Unless you are sure your tools don't have this problem, say Y.
|
|
|
+
|
|
|
config ARM_ASM_UNIFIED
|
|
|
bool
|
|
|
|
|
@@ -1644,6 +1712,18 @@ config ZBOOT_ROM
|
|
|
Say Y here if you intend to execute your compressed kernel image
|
|
|
(zImage) directly from ROM or flash. If unsure, say N.
|
|
|
|
|
|
+config ZBOOT_ROM_MMCIF
|
|
|
+ bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
|
|
|
+ depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
|
|
|
+ help
|
|
|
+ Say Y here to include experimental MMCIF loading code in the
|
|
|
+ ROM-able zImage. With this enabled it is possible to write the
|
|
|
+ the ROM-able zImage kernel image to an MMC card and boot the
|
|
|
+ kernel straight from the reset vector. At reset the processor
|
|
|
+ Mask ROM will load the first part of the the ROM-able zImage
|
|
|
+ which in turn loads the rest the kernel image to RAM using the
|
|
|
+ MMCIF hardware block.
|
|
|
+
|
|
|
config CMDLINE
|
|
|
string "Default kernel command string"
|
|
|
default ""
|
|
@@ -1877,7 +1957,7 @@ config FPE_FASTFPE
|
|
|
|
|
|
config VFP
|
|
|
bool "VFP-format floating point maths"
|
|
|
- depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
|
|
|
+ depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
|
|
|
help
|
|
|
Say Y to include VFP support code in the kernel. This is needed
|
|
|
if your hardware includes a VFP unit.
|