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@@ -35,7 +35,7 @@
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#include <linux/swap.h>
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#include <linux/pci.h>
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-static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
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+static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
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static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
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static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
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static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
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@@ -2583,7 +2583,10 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
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if (!IS_I965G(dev)) {
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int ret;
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- i915_gem_object_flush_gpu_write_domain(obj);
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+ ret = i915_gem_object_flush_gpu_write_domain(obj);
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+ if (ret != 0)
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+ return ret;
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+
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ret = i915_gem_object_wait_rendering(obj);
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if (ret != 0)
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return ret;
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@@ -2731,7 +2734,7 @@ i915_gem_clflush_object(struct drm_gem_object *obj)
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}
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/** Flushes any GPU write domain for the object if it's dirty. */
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-static void
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+static int
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i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
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{
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struct drm_device *dev = obj->dev;
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@@ -2739,17 +2742,18 @@ i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
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struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
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if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
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- return;
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+ return 0;
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/* Queue the GPU write cache flushing we need. */
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old_write_domain = obj->write_domain;
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i915_gem_flush(dev, 0, obj->write_domain);
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- (void) i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring);
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- BUG_ON(obj->write_domain);
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+ if (i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring) == 0)
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+ return -ENOMEM;
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trace_i915_gem_object_change_domain(obj,
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obj->read_domains,
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old_write_domain);
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+ return 0;
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}
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/** Flushes the GTT write domain for the object if it's dirty. */
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@@ -2793,9 +2797,11 @@ i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
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old_write_domain);
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}
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-void
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+int
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i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
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{
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+ int ret = 0;
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+
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switch (obj->write_domain) {
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case I915_GEM_DOMAIN_GTT:
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i915_gem_object_flush_gtt_write_domain(obj);
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@@ -2804,9 +2810,11 @@ i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
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i915_gem_object_flush_cpu_write_domain(obj);
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break;
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default:
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- i915_gem_object_flush_gpu_write_domain(obj);
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+ ret = i915_gem_object_flush_gpu_write_domain(obj);
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break;
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}
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+
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+ return ret;
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}
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/**
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@@ -2826,7 +2834,10 @@ i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
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if (obj_priv->gtt_space == NULL)
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return -EINVAL;
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- i915_gem_object_flush_gpu_write_domain(obj);
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+ ret = i915_gem_object_flush_gpu_write_domain(obj);
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+ if (ret != 0)
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+ return ret;
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+
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/* Wait on any GPU rendering and flushing to occur. */
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ret = i915_gem_object_wait_rendering(obj);
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if (ret != 0)
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@@ -2876,7 +2887,9 @@ i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
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if (obj_priv->gtt_space == NULL)
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return -EINVAL;
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- i915_gem_object_flush_gpu_write_domain(obj);
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+ ret = i915_gem_object_flush_gpu_write_domain(obj);
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+ if (ret)
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+ return ret;
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/* Wait on any GPU rendering and flushing to occur. */
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if (obj_priv->active) {
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@@ -2924,7 +2937,10 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
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uint32_t old_write_domain, old_read_domains;
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int ret;
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- i915_gem_object_flush_gpu_write_domain(obj);
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+ ret = i915_gem_object_flush_gpu_write_domain(obj);
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+ if (ret)
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+ return ret;
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+
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/* Wait on any GPU rendering and flushing to occur. */
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ret = i915_gem_object_wait_rendering(obj);
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if (ret != 0)
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@@ -3214,7 +3230,10 @@ i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
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if (offset == 0 && size == obj->size)
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return i915_gem_object_set_to_cpu_domain(obj, 0);
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- i915_gem_object_flush_gpu_write_domain(obj);
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+ ret = i915_gem_object_flush_gpu_write_domain(obj);
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+ if (ret)
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+ return ret;
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+
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/* Wait on any GPU rendering and flushing to occur. */
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ret = i915_gem_object_wait_rendering(obj);
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if (ret != 0)
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