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@@ -72,7 +72,7 @@ static unsigned long sh_clk_div6_recalc(struct clk *clk)
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clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
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table, NULL);
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- idx = __raw_readl(clk->enable_reg) & 0x003f;
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+ idx = ioread32(clk->mapped_reg) & 0x003f;
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return clk->freq_table[idx].frequency;
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}
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@@ -98,10 +98,10 @@ static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
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if (ret < 0)
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return ret;
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- value = __raw_readl(clk->enable_reg) &
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+ value = ioread32(clk->mapped_reg) &
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~(((1 << clk->src_width) - 1) << clk->src_shift);
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- __raw_writel(value | (i << clk->src_shift), clk->enable_reg);
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+ iowrite32(value | (i << clk->src_shift), clk->mapped_reg);
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/* Rebuild the frequency table */
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clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
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@@ -119,10 +119,10 @@ static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate)
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if (idx < 0)
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return idx;
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- value = __raw_readl(clk->enable_reg);
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+ value = ioread32(clk->mapped_reg);
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value &= ~0x3f;
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value |= idx;
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- __raw_writel(value, clk->enable_reg);
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+ iowrite32(value, clk->mapped_reg);
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return 0;
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}
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@@ -133,9 +133,9 @@ static int sh_clk_div6_enable(struct clk *clk)
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ret = sh_clk_div6_set_rate(clk, clk->rate);
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if (ret == 0) {
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- value = __raw_readl(clk->enable_reg);
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+ value = ioread32(clk->mapped_reg);
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value &= ~0x100; /* clear stop bit to enable clock */
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- __raw_writel(value, clk->enable_reg);
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+ iowrite32(value, clk->mapped_reg);
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}
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return ret;
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}
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@@ -144,10 +144,10 @@ static void sh_clk_div6_disable(struct clk *clk)
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{
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unsigned long value;
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- value = __raw_readl(clk->enable_reg);
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+ value = ioread32(clk->mapped_reg);
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value |= 0x100; /* stop clock */
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value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */
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- __raw_writel(value, clk->enable_reg);
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+ iowrite32(value, clk->mapped_reg);
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}
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static struct clk_ops sh_clk_div6_clk_ops = {
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@@ -182,7 +182,7 @@ static int __init sh_clk_init_parent(struct clk *clk)
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return -EINVAL;
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}
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- val = (__raw_readl(clk->enable_reg) >> clk->src_shift);
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+ val = (ioread32(clk->mapped_reg) >> clk->src_shift);
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val &= (1 << clk->src_width) - 1;
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if (val >= clk->parent_num) {
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