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@@ -156,6 +156,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
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#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
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#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
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#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
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#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
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#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
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#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
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+#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000)
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/*
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/*
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* Add the 64-bit processor unique features in the top half of the word;
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* Add the 64-bit processor unique features in the top half of the word;
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@@ -369,43 +370,43 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
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CPU_FTR_NODSISRALIGN)
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CPU_FTR_NODSISRALIGN)
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#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
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#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \
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- CPU_FTR_L2CSR)
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+ CPU_FTR_L2CSR | CPU_FTR_LWSYNC)
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#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
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#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
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/* 64-bit CPUs */
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/* 64-bit CPUs */
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-#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
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+#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
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CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
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-#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
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+#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
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CPU_FTR_MMCRA | CPU_FTR_CTRL)
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CPU_FTR_MMCRA | CPU_FTR_CTRL)
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-#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | \
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+#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_MMCRA)
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CPU_FTR_MMCRA)
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-#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | \
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+#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
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-#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | \
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+#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
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CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
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CPU_FTR_PURR)
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CPU_FTR_PURR)
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-#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | \
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+#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
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CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
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CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
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CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
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CPU_FTR_DSCR)
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CPU_FTR_DSCR)
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-#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | \
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+#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
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CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
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CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
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CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
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CPU_FTR_DSCR)
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CPU_FTR_DSCR)
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-#define CPU_FTRS_CELL (CPU_FTR_USE_TB | \
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+#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
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CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
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-#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
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+#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
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CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
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CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
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