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@@ -22,7 +22,8 @@ static struct eisa_root_device pci_eisa_root;
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static int __init pci_eisa_init(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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- int rc;
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+ int rc, i;
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+ struct resource *res, *bus_res = NULL;
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if ((rc = pci_enable_device (pdev))) {
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printk (KERN_ERR "pci_eisa : Could not enable device %s\n",
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@@ -30,9 +31,30 @@ static int __init pci_eisa_init(struct pci_dev *pdev,
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return rc;
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}
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+ /*
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+ * The Intel 82375 PCI-EISA bridge is a subtractive-decode PCI
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+ * device, so the resources available on EISA are the same as those
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+ * available on the 82375 bus. This works the same as a PCI-PCI
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+ * bridge in subtractive-decode mode (see pci_read_bridge_bases()).
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+ * We assume other PCI-EISA bridges are similar.
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+ *
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+ * eisa_root_register() can only deal with a single io port resource,
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+ * so we use the first valid io port resource.
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+ */
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+ pci_bus_for_each_resource(pdev->bus, res, i)
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+ if (res && (res->flags & IORESOURCE_IO)) {
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+ bus_res = res;
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+ break;
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+ }
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+
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+ if (!bus_res) {
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+ dev_err(&pdev->dev, "No resources available\n");
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+ return -1;
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+ }
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+
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pci_eisa_root.dev = &pdev->dev;
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- pci_eisa_root.res = pdev->bus->resource[0];
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- pci_eisa_root.bus_base_addr = pdev->bus->resource[0]->start;
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+ pci_eisa_root.res = bus_res;
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+ pci_eisa_root.bus_base_addr = bus_res->start;
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pci_eisa_root.slots = EISA_MAX_SLOTS;
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pci_eisa_root.dma_mask = pdev->dma_mask;
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dev_set_drvdata(pci_eisa_root.dev, &pci_eisa_root);
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