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@@ -33,4 +33,16 @@
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#define APMU_FNRST_DIS (1 << 1)
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#define APMU_AXIRST_DIS (1 << 0)
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+/* Wake Clear Register */
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+#define APMU_WAKE_CLR APMU_REG(0x07c)
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+
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+#define APMU_PXA168_KP_WAKE_CLR (1 << 7)
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+#define APMU_PXA168_CFI_WAKE_CLR (1 << 6)
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+#define APMU_PXA168_XD_WAKE_CLR (1 << 5)
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+#define APMU_PXA168_MSP_WAKE_CLR (1 << 4)
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+#define APMU_PXA168_SD4_WAKE_CLR (1 << 3)
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+#define APMU_PXA168_SD3_WAKE_CLR (1 << 2)
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+#define APMU_PXA168_SD2_WAKE_CLR (1 << 1)
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+#define APMU_PXA168_SD1_WAKE_CLR (1 << 0)
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+
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#endif /* __ASM_MACH_REGS_APMU_H */
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Mark F. Brown