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@@ -418,6 +418,240 @@ u8 ata_altstatus(struct ata_port *ap)
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return inb(ap->ioaddr.altstatus_addr);
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}
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+/**
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+ * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction
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+ * @qc: Info associated with this ATA transaction.
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+ *
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+ * LOCKING:
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+ * spin_lock_irqsave(host_set lock)
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+ */
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+
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+static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc)
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+{
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+ struct ata_port *ap = qc->ap;
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+ unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
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+ u8 dmactl;
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+ void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
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+
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+ /* load PRD table addr. */
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+ mb(); /* make sure PRD table writes are visible to controller */
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+ writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
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+
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+ /* specify data direction, triple-check start bit is clear */
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+ dmactl = readb(mmio + ATA_DMA_CMD);
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+ dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
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+ if (!rw)
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+ dmactl |= ATA_DMA_WR;
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+ writeb(dmactl, mmio + ATA_DMA_CMD);
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+
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+ /* issue r/w command */
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+ ap->ops->exec_command(ap, &qc->tf);
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+}
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+
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+/**
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+ * ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction
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+ * @qc: Info associated with this ATA transaction.
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+ *
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+ * LOCKING:
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+ * spin_lock_irqsave(host_set lock)
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+ */
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+
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+static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc)
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+{
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+ struct ata_port *ap = qc->ap;
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+ void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
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+ u8 dmactl;
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+
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+ /* start host DMA transaction */
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+ dmactl = readb(mmio + ATA_DMA_CMD);
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+ writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
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+
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+ /* Strictly, one may wish to issue a readb() here, to
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+ * flush the mmio write. However, control also passes
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+ * to the hardware at this point, and it will interrupt
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+ * us when we are to resume control. So, in effect,
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+ * we don't care when the mmio write flushes.
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+ * Further, a read of the DMA status register _immediately_
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+ * following the write may not be what certain flaky hardware
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+ * is expected, so I think it is best to not add a readb()
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+ * without first all the MMIO ATA cards/mobos.
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+ * Or maybe I'm just being paranoid.
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+ */
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+}
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+
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+/**
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+ * ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO)
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+ * @qc: Info associated with this ATA transaction.
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+ *
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+ * LOCKING:
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+ * spin_lock_irqsave(host_set lock)
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+ */
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+
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+static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc)
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+{
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+ struct ata_port *ap = qc->ap;
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+ unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
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+ u8 dmactl;
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+
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+ /* load PRD table addr. */
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+ outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
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+
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+ /* specify data direction, triple-check start bit is clear */
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+ dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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+ dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
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+ if (!rw)
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+ dmactl |= ATA_DMA_WR;
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+ outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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+
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+ /* issue r/w command */
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+ ap->ops->exec_command(ap, &qc->tf);
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+}
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+
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+/**
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+ * ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO)
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+ * @qc: Info associated with this ATA transaction.
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+ *
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+ * LOCKING:
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+ * spin_lock_irqsave(host_set lock)
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+ */
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+
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+static void ata_bmdma_start_pio (struct ata_queued_cmd *qc)
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+{
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+ struct ata_port *ap = qc->ap;
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+ u8 dmactl;
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+
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+ /* start host DMA transaction */
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+ dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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+ outb(dmactl | ATA_DMA_START,
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+ ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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+}
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+
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+
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+/**
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+ * ata_bmdma_start - Start a PCI IDE BMDMA transaction
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+ * @qc: Info associated with this ATA transaction.
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+ *
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+ * Writes the ATA_DMA_START flag to the DMA command register.
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+ *
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+ * May be used as the bmdma_start() entry in ata_port_operations.
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+ *
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+ * LOCKING:
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+ * spin_lock_irqsave(host_set lock)
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+ */
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+void ata_bmdma_start(struct ata_queued_cmd *qc)
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+{
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+ if (qc->ap->flags & ATA_FLAG_MMIO)
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+ ata_bmdma_start_mmio(qc);
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+ else
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+ ata_bmdma_start_pio(qc);
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+}
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+
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+
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+/**
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+ * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
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+ * @qc: Info associated with this ATA transaction.
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+ *
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+ * Writes address of PRD table to device's PRD Table Address
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+ * register, sets the DMA control register, and calls
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+ * ops->exec_command() to start the transfer.
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+ *
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+ * May be used as the bmdma_setup() entry in ata_port_operations.
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+ *
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+ * LOCKING:
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+ * spin_lock_irqsave(host_set lock)
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+ */
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+void ata_bmdma_setup(struct ata_queued_cmd *qc)
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+{
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+ if (qc->ap->flags & ATA_FLAG_MMIO)
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+ ata_bmdma_setup_mmio(qc);
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+ else
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+ ata_bmdma_setup_pio(qc);
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+}
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+
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+
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+/**
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+ * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
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+ * @ap: Port associated with this ATA transaction.
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+ *
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+ * Clear interrupt and error flags in DMA status register.
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+ *
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+ * May be used as the irq_clear() entry in ata_port_operations.
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+ *
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+ * LOCKING:
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+ * spin_lock_irqsave(host_set lock)
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+ */
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+
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+void ata_bmdma_irq_clear(struct ata_port *ap)
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+{
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+ if (!ap->ioaddr.bmdma_addr)
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+ return;
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+
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+ if (ap->flags & ATA_FLAG_MMIO) {
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+ void __iomem *mmio =
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+ ((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS;
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+ writeb(readb(mmio), mmio);
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+ } else {
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+ unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS;
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+ outb(inb(addr), addr);
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+ }
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+}
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+
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+
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+/**
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+ * ata_bmdma_status - Read PCI IDE BMDMA status
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+ * @ap: Port associated with this ATA transaction.
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+ *
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+ * Read and return BMDMA status register.
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+ *
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+ * May be used as the bmdma_status() entry in ata_port_operations.
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+ *
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+ * LOCKING:
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+ * spin_lock_irqsave(host_set lock)
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+ */
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+
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+u8 ata_bmdma_status(struct ata_port *ap)
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+{
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+ u8 host_stat;
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+ if (ap->flags & ATA_FLAG_MMIO) {
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+ void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
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+ host_stat = readb(mmio + ATA_DMA_STATUS);
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+ } else
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+ host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
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+ return host_stat;
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+}
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+
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+
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+/**
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+ * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
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+ * @qc: Command we are ending DMA for
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+ *
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+ * Clears the ATA_DMA_START flag in the dma control register
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+ *
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+ * May be used as the bmdma_stop() entry in ata_port_operations.
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+ *
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+ * LOCKING:
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+ * spin_lock_irqsave(host_set lock)
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+ */
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+
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+void ata_bmdma_stop(struct ata_queued_cmd *qc)
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+{
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+ struct ata_port *ap = qc->ap;
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+ if (ap->flags & ATA_FLAG_MMIO) {
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+ void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
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+
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+ /* clear start/stop bit */
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+ writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
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+ mmio + ATA_DMA_CMD);
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+ } else {
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+ /* clear start/stop bit */
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+ outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START,
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+ ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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+ }
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+
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+ /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
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+ ata_altstatus(ap); /* dummy read */
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+}
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+
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#ifdef CONFIG_PCI
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static struct ata_probe_ent *
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ata_probe_ent_alloc(struct device *dev, const struct ata_port_info *port)
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Jeff Garzik