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@@ -18,7 +18,9 @@
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* 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat)
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* 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat)
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* 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA
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* 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA
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* 27-Aug-2005 Ben Dooks Add clock-slow info
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* 27-Aug-2005 Ben Dooks Add clock-slow info
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- */
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+ * 20-Oct-2005 Ben Dooks Fixed overflow in PLL (Guillaume Gourat)
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+ * 20-Oct-2005 Ben Dooks Add masks for DCLK (Guillaume Gourat)
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+*/
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#ifndef __ASM_ARM_REGS_CLOCK
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#ifndef __ASM_ARM_REGS_CLOCK
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#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
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#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
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@@ -66,11 +68,16 @@
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#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1)
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#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1)
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#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
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#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
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#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
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#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
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+#define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4)
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+#define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8)
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#define S3C2410_DCLKCON_DCLK1EN (1<<16)
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#define S3C2410_DCLKCON_DCLK1EN (1<<16)
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#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17)
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#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17)
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#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17)
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#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17)
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#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
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#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
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+#define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24)
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+#define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20)
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+#define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24)
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#define S3C2410_CLKDIVN_PDIVN (1<<0)
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#define S3C2410_CLKDIVN_PDIVN (1<<0)
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#define S3C2410_CLKDIVN_HDIVN (1<<1)
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#define S3C2410_CLKDIVN_HDIVN (1<<1)
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@@ -83,10 +90,13 @@
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLY__
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+#include <asm/div64.h>
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+
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static inline unsigned int
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static inline unsigned int
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-s3c2410_get_pll(int pllval, int baseclk)
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+s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
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{
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{
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- int mdiv, pdiv, sdiv;
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+ unsigned int mdiv, pdiv, sdiv;
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+ uint64_t fvco;
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mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
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mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
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pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
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pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
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@@ -96,7 +106,10 @@ s3c2410_get_pll(int pllval, int baseclk)
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pdiv &= S3C2410_PLLCON_PDIVMASK;
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pdiv &= S3C2410_PLLCON_PDIVMASK;
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sdiv &= S3C2410_PLLCON_SDIVMASK;
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sdiv &= S3C2410_PLLCON_SDIVMASK;
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- return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv);
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+ fvco = (uint64_t)baseclk * (mdiv + 8);
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+ do_div(fvco, (pdiv + 2) << sdiv);
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+
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+ return (unsigned int)fvco;
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}
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLY__ */
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