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@@ -0,0 +1,255 @@
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+/*
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+ * Interrupt controller support for MAX8998
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+ *
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+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
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+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ */
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+
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+#include <linux/device.h>
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+#include <linux/interrupt.h>
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+#include <linux/irq.h>
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+#include <linux/mfd/max8998-private.h>
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+
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+struct max8998_irq_data {
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+ int reg;
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+ int mask;
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+};
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+
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+static struct max8998_irq_data max8998_irqs[] = {
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+ [MAX8998_IRQ_DCINF] = {
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+ .reg = 1,
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+ .mask = MAX8998_IRQ_DCINF_MASK,
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+ },
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+ [MAX8998_IRQ_DCINR] = {
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+ .reg = 1,
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+ .mask = MAX8998_IRQ_DCINR_MASK,
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+ },
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+ [MAX8998_IRQ_JIGF] = {
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+ .reg = 1,
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+ .mask = MAX8998_IRQ_JIGF_MASK,
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+ },
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+ [MAX8998_IRQ_JIGR] = {
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+ .reg = 1,
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+ .mask = MAX8998_IRQ_JIGR_MASK,
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+ },
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+ [MAX8998_IRQ_PWRONF] = {
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+ .reg = 1,
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+ .mask = MAX8998_IRQ_PWRONF_MASK,
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+ },
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+ [MAX8998_IRQ_PWRONR] = {
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+ .reg = 1,
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+ .mask = MAX8998_IRQ_PWRONR_MASK,
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+ },
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+ [MAX8998_IRQ_WTSREVNT] = {
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+ .reg = 2,
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+ .mask = MAX8998_IRQ_WTSREVNT_MASK,
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+ },
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+ [MAX8998_IRQ_SMPLEVNT] = {
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+ .reg = 2,
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+ .mask = MAX8998_IRQ_SMPLEVNT_MASK,
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+ },
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+ [MAX8998_IRQ_ALARM1] = {
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+ .reg = 2,
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+ .mask = MAX8998_IRQ_ALARM1_MASK,
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+ },
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+ [MAX8998_IRQ_ALARM0] = {
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+ .reg = 2,
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+ .mask = MAX8998_IRQ_ALARM0_MASK,
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+ },
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+ [MAX8998_IRQ_ONKEY1S] = {
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+ .reg = 3,
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+ .mask = MAX8998_IRQ_ONKEY1S_MASK,
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+ },
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+ [MAX8998_IRQ_TOPOFFR] = {
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+ .reg = 3,
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+ .mask = MAX8998_IRQ_TOPOFFR_MASK,
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+ },
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+ [MAX8998_IRQ_DCINOVPR] = {
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+ .reg = 3,
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+ .mask = MAX8998_IRQ_DCINOVPR_MASK,
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+ },
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+ [MAX8998_IRQ_CHGRSTF] = {
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+ .reg = 3,
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+ .mask = MAX8998_IRQ_CHGRSTF_MASK,
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+ },
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+ [MAX8998_IRQ_DONER] = {
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+ .reg = 3,
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+ .mask = MAX8998_IRQ_DONER_MASK,
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+ },
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+ [MAX8998_IRQ_CHGFAULT] = {
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+ .reg = 3,
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+ .mask = MAX8998_IRQ_CHGFAULT_MASK,
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+ },
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+ [MAX8998_IRQ_LOBAT1] = {
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+ .reg = 4,
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+ .mask = MAX8998_IRQ_LOBAT1_MASK,
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+ },
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+ [MAX8998_IRQ_LOBAT2] = {
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+ .reg = 4,
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+ .mask = MAX8998_IRQ_LOBAT2_MASK,
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+ },
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+};
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+
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+static inline struct max8998_irq_data *
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+irq_to_max8998_irq(struct max8998_dev *max8998, int irq)
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+{
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+ return &max8998_irqs[irq - max8998->irq_base];
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+}
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+
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+static void max8998_irq_lock(unsigned int irq)
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+{
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+ struct max8998_dev *max8998 = get_irq_chip_data(irq);
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+
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+ mutex_lock(&max8998->irqlock);
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+}
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+
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+static void max8998_irq_sync_unlock(unsigned int irq)
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+{
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+ struct max8998_dev *max8998 = get_irq_chip_data(irq);
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(max8998->irq_masks_cur); i++) {
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+ /*
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+ * If there's been a change in the mask write it back
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+ * to the hardware.
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+ */
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+ if (max8998->irq_masks_cur[i] != max8998->irq_masks_cache[i]) {
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+ max8998->irq_masks_cache[i] = max8998->irq_masks_cur[i];
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+ max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i,
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+ max8998->irq_masks_cur[i]);
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+ }
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+ }
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+
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+ mutex_unlock(&max8998->irqlock);
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+}
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+
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+static void max8998_irq_unmask(unsigned int irq)
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+{
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+ struct max8998_dev *max8998 = get_irq_chip_data(irq);
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+ struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998, irq);
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+
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+ max8998->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
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+}
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+
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+static void max8998_irq_mask(unsigned int irq)
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+{
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+ struct max8998_dev *max8998 = get_irq_chip_data(irq);
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+ struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998, irq);
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+
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+ max8998->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
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+}
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+
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+static struct irq_chip max8998_irq_chip = {
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+ .name = "max8998",
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+ .bus_lock = max8998_irq_lock,
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+ .bus_sync_unlock = max8998_irq_sync_unlock,
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+ .mask = max8998_irq_mask,
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+ .unmask = max8998_irq_unmask,
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+};
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+
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+static irqreturn_t max8998_irq_thread(int irq, void *data)
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+{
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+ struct max8998_dev *max8998 = data;
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+ u8 irq_reg[MAX8998_NUM_IRQ_REGS];
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+ int ret;
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+ int i;
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+
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+ ret = max8998_bulk_read(max8998->i2c, MAX8998_REG_IRQ1,
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+ MAX8998_NUM_IRQ_REGS, irq_reg);
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+ if (ret < 0) {
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+ dev_err(max8998->dev, "Failed to read interrupt register: %d\n",
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+ ret);
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+ return IRQ_NONE;
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+ }
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+
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+ /* Apply masking */
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+ for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++)
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+ irq_reg[i] &= ~max8998->irq_masks_cur[i];
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+
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+ /* Report */
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+ for (i = 0; i < MAX8998_IRQ_NR; i++) {
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+ if (irq_reg[max8998_irqs[i].reg - 1] & max8998_irqs[i].mask)
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+ handle_nested_irq(max8998->irq_base + i);
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+ }
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+
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+ return IRQ_HANDLED;
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+}
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+
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+int max8998_irq_init(struct max8998_dev *max8998)
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+{
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+ int i;
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+ int cur_irq;
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+ int ret;
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+
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+ if (!max8998->irq) {
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+ dev_warn(max8998->dev,
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+ "No interrupt specified, no interrupts\n");
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+ max8998->irq_base = 0;
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+ return 0;
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+ }
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+
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+ if (!max8998->irq_base) {
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+ dev_err(max8998->dev,
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+ "No interrupt base specified, no interrupts\n");
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+ return 0;
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+ }
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+
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+ mutex_init(&max8998->irqlock);
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+
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+ /* Mask the individual interrupt sources */
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+ for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++) {
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+ max8998->irq_masks_cur[i] = 0xff;
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+ max8998->irq_masks_cache[i] = 0xff;
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+ max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i, 0xff);
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+ }
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+
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+ max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM1, 0xff);
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+ max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM2, 0xff);
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+
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+ /* register with genirq */
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+ for (i = 0; i < MAX8998_IRQ_NR; i++) {
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+ cur_irq = i + max8998->irq_base;
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+ set_irq_chip_data(cur_irq, max8998);
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+ set_irq_chip_and_handler(cur_irq, &max8998_irq_chip,
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+ handle_edge_irq);
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+ set_irq_nested_thread(cur_irq, 1);
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+#ifdef CONFIG_ARM
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+ set_irq_flags(cur_irq, IRQF_VALID);
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+#else
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+ set_irq_noprobe(cur_irq);
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+#endif
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+ }
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+
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+ ret = request_threaded_irq(max8998->irq, NULL, max8998_irq_thread,
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+ IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
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+ "max8998-irq", max8998);
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+ if (ret) {
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+ dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
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+ max8998->irq, ret);
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+ return ret;
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+ }
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+
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+ if (!max8998->ono)
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+ return 0;
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+
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+ ret = request_threaded_irq(max8998->ono, NULL, max8998_irq_thread,
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+ IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
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+ IRQF_ONESHOT, "max8998-ono", max8998);
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+ if (ret)
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+ dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
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+ max8998->ono, ret);
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+
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+ return 0;
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+}
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+
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+void max8998_irq_exit(struct max8998_dev *max8998)
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+{
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+ if (max8998->irq)
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+ free_irq(max8998->irq, max8998);
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+}
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Joonyoung Shim