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@@ -281,29 +281,25 @@ static inline int eilvt_is_available(int offset)
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static inline int ibs_eilvt_valid(void)
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{
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- u64 val;
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int offset;
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+ u64 val;
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rdmsrl(MSR_AMD64_IBSCTL, val);
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+ offset = val & IBSCTL_LVT_OFFSET_MASK;
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+
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if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
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- pr_err(FW_BUG "cpu %d, invalid IBS "
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- "interrupt offset %d (MSR%08X=0x%016llx)",
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- smp_processor_id(), offset,
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- MSR_AMD64_IBSCTL, val);
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+ pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
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+ smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
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return 0;
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}
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- offset = val & IBSCTL_LVT_OFFSET_MASK;
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-
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- if (eilvt_is_available(offset))
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- return !0;
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-
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- pr_err(FW_BUG "cpu %d, IBS interrupt offset %d "
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- "not available (MSR%08X=0x%016llx)",
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- smp_processor_id(), offset,
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- MSR_AMD64_IBSCTL, val);
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+ if (!eilvt_is_available(offset)) {
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+ pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
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+ smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
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+ return 0;
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+ }
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- return 0;
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+ return 1;
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}
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static inline int get_ibs_offset(void)
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