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@@ -16,6 +16,7 @@
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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+#include <linux/clkdev.h>
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#include <asm/div64.h>
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@@ -31,12 +32,21 @@ struct clk {
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unsigned long rate;
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};
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-static struct clk ath79_ref_clk;
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-static struct clk ath79_cpu_clk;
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-static struct clk ath79_ddr_clk;
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-static struct clk ath79_ahb_clk;
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-static struct clk ath79_wdt_clk;
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-static struct clk ath79_uart_clk;
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+static void __init ath79_add_sys_clkdev(const char *id, unsigned long rate)
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+{
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+ struct clk *clk;
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+ int err;
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+
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+ clk = kzalloc(sizeof(*clk), GFP_KERNEL);
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+ if (!clk)
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+ panic("failed to allocate %s clock structure", id);
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+
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+ clk->rate = rate;
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+
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+ err = clk_register_clkdev(clk, id, NULL);
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+ if (err)
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+ panic("unable to register %s clock device", id);
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+}
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static void __init ar71xx_clocks_init(void)
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{
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@@ -64,13 +74,13 @@ static void __init ar71xx_clocks_init(void)
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div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
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ahb_rate = cpu_rate / div;
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- ath79_ref_clk.rate = ref_rate;
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- ath79_cpu_clk.rate = cpu_rate;
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- ath79_ddr_clk.rate = ddr_rate;
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- ath79_ahb_clk.rate = ahb_rate;
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+ ath79_add_sys_clkdev("ref", ref_rate);
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+ ath79_add_sys_clkdev("cpu", cpu_rate);
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+ ath79_add_sys_clkdev("ddr", ddr_rate);
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+ ath79_add_sys_clkdev("ahb", ahb_rate);
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- ath79_wdt_clk.rate = ath79_ahb_clk.rate;
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- ath79_uart_clk.rate = ath79_ahb_clk.rate;
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+ clk_add_alias("wdt", NULL, "ahb", NULL);
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+ clk_add_alias("uart", NULL, "ahb", NULL);
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}
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static void __init ar724x_clocks_init(void)
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@@ -100,13 +110,13 @@ static void __init ar724x_clocks_init(void)
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div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
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ahb_rate = cpu_rate / div;
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- ath79_ref_clk.rate = ref_rate;
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- ath79_cpu_clk.rate = cpu_rate;
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- ath79_ddr_clk.rate = ddr_rate;
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- ath79_ahb_clk.rate = ahb_rate;
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+ ath79_add_sys_clkdev("ref", ref_rate);
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+ ath79_add_sys_clkdev("cpu", cpu_rate);
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+ ath79_add_sys_clkdev("ddr", ddr_rate);
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+ ath79_add_sys_clkdev("ahb", ahb_rate);
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- ath79_wdt_clk.rate = ath79_ahb_clk.rate;
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- ath79_uart_clk.rate = ath79_ahb_clk.rate;
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+ clk_add_alias("wdt", NULL, "ahb", NULL);
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+ clk_add_alias("uart", NULL, "ahb", NULL);
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}
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static void __init ar913x_clocks_init(void)
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@@ -133,13 +143,13 @@ static void __init ar913x_clocks_init(void)
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div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;
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ahb_rate = cpu_rate / div;
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- ath79_ref_clk.rate = ref_rate;
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- ath79_cpu_clk.rate = cpu_rate;
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- ath79_ddr_clk.rate = ddr_rate;
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- ath79_ahb_clk.rate = ahb_rate;
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+ ath79_add_sys_clkdev("ref", ref_rate);
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+ ath79_add_sys_clkdev("cpu", cpu_rate);
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+ ath79_add_sys_clkdev("ddr", ddr_rate);
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+ ath79_add_sys_clkdev("ahb", ahb_rate);
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- ath79_wdt_clk.rate = ath79_ahb_clk.rate;
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- ath79_uart_clk.rate = ath79_ahb_clk.rate;
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+ clk_add_alias("wdt", NULL, "ahb", NULL);
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+ clk_add_alias("uart", NULL, "ahb", NULL);
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}
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static void __init ar933x_clocks_init(void)
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@@ -195,13 +205,13 @@ static void __init ar933x_clocks_init(void)
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ahb_rate = freq / t;
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}
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- ath79_ref_clk.rate = ref_rate;
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- ath79_cpu_clk.rate = cpu_rate;
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- ath79_ddr_clk.rate = ddr_rate;
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- ath79_ahb_clk.rate = ahb_rate;
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+ ath79_add_sys_clkdev("ref", ref_rate);
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+ ath79_add_sys_clkdev("cpu", cpu_rate);
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+ ath79_add_sys_clkdev("ddr", ddr_rate);
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+ ath79_add_sys_clkdev("ahb", ahb_rate);
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- ath79_wdt_clk.rate = ath79_ahb_clk.rate;
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- ath79_uart_clk.rate = ath79_ref_clk.rate;
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+ clk_add_alias("wdt", NULL, "ahb", NULL);
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+ clk_add_alias("uart", NULL, "ref", NULL);
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}
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static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
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@@ -329,13 +339,13 @@ static void __init ar934x_clocks_init(void)
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else
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ahb_rate = cpu_pll / (postdiv + 1);
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- ath79_ref_clk.rate = ref_rate;
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- ath79_cpu_clk.rate = cpu_rate;
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- ath79_ddr_clk.rate = ddr_rate;
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- ath79_ahb_clk.rate = ahb_rate;
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+ ath79_add_sys_clkdev("ref", ref_rate);
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+ ath79_add_sys_clkdev("cpu", cpu_rate);
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+ ath79_add_sys_clkdev("ddr", ddr_rate);
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+ ath79_add_sys_clkdev("ahb", ahb_rate);
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- ath79_wdt_clk.rate = ath79_ref_clk.rate;
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- ath79_uart_clk.rate = ath79_ref_clk.rate;
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+ clk_add_alias("wdt", NULL, "ref", NULL);
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+ clk_add_alias("uart", NULL, "ref", NULL);
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iounmap(dpll_base);
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}
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@@ -416,13 +426,13 @@ static void __init qca955x_clocks_init(void)
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else
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ahb_rate = cpu_pll / (postdiv + 1);
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- ath79_ref_clk.rate = ref_rate;
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- ath79_cpu_clk.rate = cpu_rate;
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- ath79_ddr_clk.rate = ddr_rate;
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- ath79_ahb_clk.rate = ahb_rate;
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+ ath79_add_sys_clkdev("ref", ref_rate);
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+ ath79_add_sys_clkdev("cpu", cpu_rate);
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+ ath79_add_sys_clkdev("ddr", ddr_rate);
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+ ath79_add_sys_clkdev("ahb", ahb_rate);
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- ath79_wdt_clk.rate = ath79_ref_clk.rate;
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- ath79_uart_clk.rate = ath79_ref_clk.rate;
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+ clk_add_alias("wdt", NULL, "ref", NULL);
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+ clk_add_alias("uart", NULL, "ref", NULL);
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}
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void __init ath79_clocks_init(void)
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@@ -462,30 +472,6 @@ ath79_get_sys_clk_rate(const char *id)
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/*
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* Linux clock API
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*/
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-struct clk *clk_get(struct device *dev, const char *id)
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-{
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- if (!strcmp(id, "ref"))
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- return &ath79_ref_clk;
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-
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- if (!strcmp(id, "cpu"))
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- return &ath79_cpu_clk;
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-
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- if (!strcmp(id, "ddr"))
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- return &ath79_ddr_clk;
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-
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- if (!strcmp(id, "ahb"))
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- return &ath79_ahb_clk;
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-
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- if (!strcmp(id, "wdt"))
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- return &ath79_wdt_clk;
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-
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- if (!strcmp(id, "uart"))
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- return &ath79_uart_clk;
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-
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- return ERR_PTR(-ENOENT);
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-}
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-EXPORT_SYMBOL(clk_get);
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-
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int clk_enable(struct clk *clk)
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{
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return 0;
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@@ -502,8 +488,3 @@ unsigned long clk_get_rate(struct clk *clk)
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return clk->rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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-
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-void clk_put(struct clk *clk)
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-{
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-}
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-EXPORT_SYMBOL(clk_put);
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