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@@ -1380,20 +1380,10 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
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}
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/* 24K */
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-#define IS_UNSUPPORTED_24K_EVENT(r, b) \
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- ((b) == 12 || (r) == 151 || (r) == 152 || (b) == 26 || \
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- (b) == 27 || (r) == 28 || (r) == 158 || (b) == 31 || \
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- (b) == 32 || (b) == 34 || (b) == 36 || (r) == 168 || \
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- (r) == 172 || (b) == 47 || ((b) >= 56 && (b) <= 63) || \
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- ((b) >= 68 && (b) <= 127))
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#define IS_BOTH_COUNTERS_24K_EVENT(b) \
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((b) == 0 || (b) == 1 || (b) == 11)
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/* 34K */
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-#define IS_UNSUPPORTED_34K_EVENT(r, b) \
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- ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 36 || \
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- (b) == 38 || (r) == 175 || ((b) >= 56 && (b) <= 63) || \
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- ((b) >= 68 && (b) <= 127))
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#define IS_BOTH_COUNTERS_34K_EVENT(b) \
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((b) == 0 || (b) == 1 || (b) == 11)
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#ifdef CONFIG_MIPS_MT_SMP
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@@ -1406,20 +1396,10 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
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#endif
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/* 74K */
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-#define IS_UNSUPPORTED_74K_EVENT(r, b) \
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- ((r) == 5 || ((r) >= 135 && (r) <= 137) || \
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- ((b) >= 10 && (b) <= 12) || (b) == 22 || (b) == 27 || \
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- (b) == 33 || (b) == 34 || ((b) >= 47 && (b) <= 49) || \
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- (r) == 178 || (b) == 55 || (b) == 57 || (b) == 60 || \
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- (b) == 61 || (r) == 62 || (r) == 191 || \
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- ((b) >= 64 && (b) <= 127))
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#define IS_BOTH_COUNTERS_74K_EVENT(b) \
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((b) == 0 || (b) == 1)
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/* 1004K */
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-#define IS_UNSUPPORTED_1004K_EVENT(r, b) \
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- ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 38 || \
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- (r) == 175 || (b) == 63 || ((b) >= 68 && (b) <= 127))
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#define IS_BOTH_COUNTERS_1004K_EVENT(b) \
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((b) == 0 || (b) == 1 || (b) == 11)
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#ifdef CONFIG_MIPS_MT_SMP
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@@ -1445,11 +1425,10 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
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unsigned int raw_id = config & 0xff;
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unsigned int base_id = raw_id & 0x7f;
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+ raw_event.event_id = base_id;
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+
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switch (current_cpu_type()) {
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case CPU_24K:
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- if (IS_UNSUPPORTED_24K_EVENT(raw_id, base_id))
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- return ERR_PTR(-EOPNOTSUPP);
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- raw_event.event_id = base_id;
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if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
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raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
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else
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@@ -1464,9 +1443,6 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
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#endif
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break;
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case CPU_34K:
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- if (IS_UNSUPPORTED_34K_EVENT(raw_id, base_id))
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- return ERR_PTR(-EOPNOTSUPP);
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- raw_event.event_id = base_id;
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if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
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raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
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else
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@@ -1482,9 +1458,6 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
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#endif
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break;
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case CPU_74K:
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- if (IS_UNSUPPORTED_74K_EVENT(raw_id, base_id))
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- return ERR_PTR(-EOPNOTSUPP);
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- raw_event.event_id = base_id;
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if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
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raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
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else
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@@ -1495,9 +1468,6 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
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#endif
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break;
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case CPU_1004K:
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- if (IS_UNSUPPORTED_1004K_EVENT(raw_id, base_id))
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- return ERR_PTR(-EOPNOTSUPP);
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- raw_event.event_id = base_id;
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if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
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raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
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else
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