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@@ -108,3 +108,85 @@ void ibm4xx_fixup_ebc_ranges(const char *ebc)
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setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32));
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}
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+
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+#define SPRN_CCR1 0x378
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+void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
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+{
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+ u32 cpu, plb, opb, ebc, tb, uart0, m, vco;
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+ u32 reg;
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+ u32 fwdva, fwdvb, fbdv, lfbdv, opbdv0, perdv0, spcid0, prbdv0, tmp;
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+
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+ mtdcr(DCRN_CPR0_ADDR, CPR0_PLLD0);
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+ reg = mfdcr(DCRN_CPR0_DATA);
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+ tmp = (reg & 0x000F0000) >> 16;
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+ fwdva = tmp ? tmp : 16;
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+ tmp = (reg & 0x00000700) >> 8;
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+ fwdvb = tmp ? tmp : 8;
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+ tmp = (reg & 0x1F000000) >> 24;
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+ fbdv = tmp ? tmp : 32;
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+ lfbdv = (reg & 0x0000007F);
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+
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+ mtdcr(DCRN_CPR0_ADDR, CPR0_OPBD0);
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+ reg = mfdcr(DCRN_CPR0_DATA);
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+ tmp = (reg & 0x03000000) >> 24;
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+ opbdv0 = tmp ? tmp : 4;
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+
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+ mtdcr(DCRN_CPR0_ADDR, CPR0_PERD0);
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+ reg = mfdcr(DCRN_CPR0_DATA);
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+ tmp = (reg & 0x07000000) >> 24;
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+ perdv0 = tmp ? tmp : 8;
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+
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+ mtdcr(DCRN_CPR0_ADDR, CPR0_PRIMBD0);
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+ reg = mfdcr(DCRN_CPR0_DATA);
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+ tmp = (reg & 0x07000000) >> 24;
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+ prbdv0 = tmp ? tmp : 8;
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+
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+ mtdcr(DCRN_CPR0_ADDR, CPR0_SCPID);
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+ reg = mfdcr(DCRN_CPR0_DATA);
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+ tmp = (reg & 0x03000000) >> 24;
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+ spcid0 = tmp ? tmp : 4;
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+
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+ /* Calculate M */
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+ mtdcr(DCRN_CPR0_ADDR, CPR0_PLLC0);
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+ reg = mfdcr(DCRN_CPR0_DATA);
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+ tmp = (reg & 0x03000000) >> 24;
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+ if (tmp == 0) { /* PLL output */
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+ tmp = (reg & 0x20000000) >> 29;
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+ if (!tmp) /* PLLOUTA */
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+ m = fbdv * lfbdv * fwdva;
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+ else
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+ m = fbdv * lfbdv * fwdvb;
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+ }
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+ else if (tmp == 1) /* CPU output */
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+ m = fbdv * fwdva;
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+ else
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+ m = perdv0 * opbdv0 * fwdvb;
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+
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+ vco = (m * sysclk) + (m >> 1);
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+ cpu = vco / fwdva;
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+ plb = vco / fwdvb / prbdv0;
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+ opb = plb / opbdv0;
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+ ebc = plb / perdv0;
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+
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+ /* FIXME */
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+ uart0 = ser_clk;
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+
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+ /* Figure out timebase. Either CPU or default TmrClk */
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+ asm volatile (
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+ "mfspr %0,%1\n"
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+ :
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+ "=&r"(reg) : "i"(SPRN_CCR1));
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+ if (reg & 0x0080)
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+ tb = 25000000; /* TmrClk is 25MHz */
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+ else
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+ tb = cpu;
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+
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+ dt_fixup_cpu_clocks(cpu, tb, 0);
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+ dt_fixup_clock("/plb", plb);
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+ dt_fixup_clock("/plb/opb", opb);
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+ dt_fixup_clock("/plb/opb/ebc", ebc);
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+ dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
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+ dt_fixup_clock("/plb/opb/serial@ef600400", uart0);
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+ dt_fixup_clock("/plb/opb/serial@ef600500", uart0);
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+ dt_fixup_clock("/plb/opb/serial@ef600600", uart0);
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+}
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