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-/*
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- * Agere Systems Inc.
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- * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
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- *
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- * Copyright © 2005 Agere Systems Inc.
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- * All rights reserved.
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- * http://www.agere.com
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- *
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- * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
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- *
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- *------------------------------------------------------------------------------
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- *
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- * et1310_phy.h - Defines, structs, enums, prototypes, etc. pertaining to the
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- * PHY.
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- *
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- *------------------------------------------------------------------------------
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- *
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- * SOFTWARE LICENSE
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- *
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- * This software is provided subject to the following terms and conditions,
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- * which you should read carefully before using the software. Using this
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- * software indicates your acceptance of these terms and conditions. If you do
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- * not agree with these terms and conditions, do not use the software.
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- *
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- * Copyright © 2005 Agere Systems Inc.
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- * All rights reserved.
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- *
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- * Redistribution and use in source or binary forms, with or without
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- * modifications, are permitted provided that the following conditions are met:
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- *
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- * . Redistributions of source code must retain the above copyright notice, this
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- * list of conditions and the following Disclaimer as comments in the code as
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- * well as in the documentation and/or other materials provided with the
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- * distribution.
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- *
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- * . Redistributions in binary form must reproduce the above copyright notice,
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- * this list of conditions and the following Disclaimer in the documentation
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- * and/or other materials provided with the distribution.
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- *
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- * . Neither the name of Agere Systems Inc. nor the names of the contributors
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- * may be used to endorse or promote products derived from this software
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- * without specific prior written permission.
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- *
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- * Disclaimer
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- *
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- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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- * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
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- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
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- * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
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- * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
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- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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- * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
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- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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- * DAMAGE.
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- *
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- */
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-
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-#ifndef _ET1310_PHY_H_
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-#define _ET1310_PHY_H_
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-
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-/*
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- * Defines for generic MII registers 0x00 -> 0x0F can be found in
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- * include/linux/mii.h
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- */
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-
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-/* some defines for modem registers that seem to be 'reserved' */
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-#define PHY_INDEX_REG 0x10
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-#define PHY_DATA_REG 0x11
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-#define PHY_MPHY_CONTROL_REG 0x12
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-
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-/* defines for specified registers */
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-#define PHY_LOOPBACK_CONTROL 0x13 /* TRU_VMI_LOOPBACK_CONTROL_1_REG 19 */
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- /* TRU_VMI_LOOPBACK_CONTROL_2_REG 20 */
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-#define PHY_REGISTER_MGMT_CONTROL 0x15 /* TRU_VMI_MI_SEQ_CONTROL_REG 21 */
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-#define PHY_CONFIG 0x16 /* TRU_VMI_CONFIGURATION_REG 22 */
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-#define PHY_PHY_CONTROL 0x17 /* TRU_VMI_PHY_CONTROL_REG 23 */
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-#define PHY_INTERRUPT_MASK 0x18 /* TRU_VMI_INTERRUPT_MASK_REG 24 */
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-#define PHY_INTERRUPT_STATUS 0x19 /* TRU_VMI_INTERRUPT_STATUS_REG 25 */
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-#define PHY_PHY_STATUS 0x1A /* TRU_VMI_PHY_STATUS_REG 26 */
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-#define PHY_LED_1 0x1B /* TRU_VMI_LED_CONTROL_1_REG 27 */
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-#define PHY_LED_2 0x1C /* TRU_VMI_LED_CONTROL_2_REG 28 */
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- /* TRU_VMI_LINK_CONTROL_REG 29 */
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- /* TRU_VMI_TIMING_CONTROL_REG */
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-
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-/* MI Register 10: Gigabit basic mode status reg(Reg 0x0A) */
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-#define ET_1000BT_MSTR_SLV 0x4000
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-
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-/* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
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-
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-/* MI Register 19: Loopback Control Reg(0x13)
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- * 15: mii_en
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- * 14: pcs_en
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- * 13: pmd_en
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- * 12: all_digital_en
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- * 11: replica_en
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- * 10: line_driver_en
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- * 9-0: reserved
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- */
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-
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-/* MI Register 20: Reserved Reg(0x14) */
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-
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-/* MI Register 21: Management Interface Control Reg(0x15)
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- * 15-11: reserved
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- * 10-4: mi_error_count
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- * 3: reserved
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- * 2: ignore_10g_fr
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- * 1: reserved
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- * 0: preamble_supress_en
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- */
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-
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-/* MI Register 22: PHY Configuration Reg(0x16)
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- * 15: crs_tx_en
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- * 14: reserved
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- * 13-12: tx_fifo_depth
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- * 11-10: speed_downshift
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- * 9: pbi_detect
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- * 8: tbi_rate
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- * 7: alternate_np
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- * 6: group_mdio_en
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- * 5: tx_clock_en
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- * 4: sys_clock_en
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- * 3: reserved
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- * 2-0: mac_if_mode
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- */
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-
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-#define ET_PHY_CONFIG_TX_FIFO_DEPTH 0x3000
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-
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-#define ET_PHY_CONFIG_FIFO_DEPTH_8 0x0000
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-#define ET_PHY_CONFIG_FIFO_DEPTH_16 0x1000
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-#define ET_PHY_CONFIG_FIFO_DEPTH_32 0x2000
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-#define ET_PHY_CONFIG_FIFO_DEPTH_64 0x3000
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-
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-/* MI Register 23: PHY CONTROL Reg(0x17)
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- * 15: reserved
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- * 14: tdr_en
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- * 13: reserved
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- * 12-11: downshift_attempts
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- * 10-6: reserved
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- * 5: jabber_10baseT
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- * 4: sqe_10baseT
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- * 3: tp_loopback_10baseT
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- * 2: preamble_gen_en
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- * 1: reserved
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- * 0: force_int
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- */
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-
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-/* MI Register 24: Interrupt Mask Reg(0x18)
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- * 15-10: reserved
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- * 9: mdio_sync_lost
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- * 8: autoneg_status
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- * 7: hi_bit_err
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- * 6: np_rx
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- * 5: err_counter_full
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- * 4: fifo_over_underflow
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- * 3: rx_status
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- * 2: link_status
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- * 1: automatic_speed
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- * 0: int_en
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- */
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-
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-#define ET_PHY_INT_MASK_AUTONEGSTAT 0x0100
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-#define ET_PHY_INT_MASK_LINKSTAT 0x0004
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-#define ET_PHY_INT_MASK_ENABLE 0x0001
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-
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-/* MI Register 25: Interrupt Status Reg(0x19)
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- * 15-10: reserved
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- * 9: mdio_sync_lost
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- * 8: autoneg_status
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- * 7: hi_bit_err
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- * 6: np_rx
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- * 5: err_counter_full
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- * 4: fifo_over_underflow
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- * 3: rx_status
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- * 2: link_status
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- * 1: automatic_speed
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- * 0: int_en
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- */
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-
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-/* MI Register 26: PHY Status Reg(0x1A)
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- * 15: reserved
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- * 14-13: autoneg_fault
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- * 12: autoneg_status
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- * 11: mdi_x_status
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- * 10: polarity_status
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- * 9-8: speed_status
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- * 7: duplex_status
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- * 6: link_status
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- * 5: tx_status
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- * 4: rx_status
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- * 3: collision_status
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- * 2: autoneg_en
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- * 1: pause_en
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- * 0: asymmetric_dir
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- */
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-#define ET_PHY_AUTONEG_STATUS 0x1000
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-#define ET_PHY_POLARITY_STATUS 0x0400
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-#define ET_PHY_SPEED_STATUS 0x0300
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-#define ET_PHY_DUPLEX_STATUS 0x0080
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-#define ET_PHY_LSTATUS 0x0040
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-#define ET_PHY_AUTONEG_ENABLE 0x0020
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-
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-/* MI Register 27: LED Control Reg 1(0x1B)
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- * 15-14: reserved
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- * 13-12: led_dup_indicate
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- * 11-10: led_10baseT
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- * 9-8: led_collision
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- * 7-4: reserved
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- * 3-2: pulse_dur
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- * 1: pulse_stretch1
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- * 0: pulse_stretch0
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- */
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-
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-/* MI Register 28: LED Control Reg 2(0x1C)
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- * 15-12: led_link
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- * 11-8: led_tx_rx
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- * 7-4: led_100BaseTX
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- * 3-0: led_1000BaseT
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- */
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-#define ET_LED2_LED_LINK 0xF000
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-#define ET_LED2_LED_TXRX 0x0F00
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-#define ET_LED2_LED_100TX 0x00F0
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-#define ET_LED2_LED_1000T 0x000F
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-
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-/* defines for LED control reg 2 values */
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-#define LED_VAL_1000BT 0x0
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-#define LED_VAL_100BTX 0x1
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-#define LED_VAL_10BT 0x2
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-#define LED_VAL_1000BT_100BTX 0x3 /* 1000BT on, 100BTX blink */
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-#define LED_VAL_LINKON 0x4
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-#define LED_VAL_TX 0x5
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-#define LED_VAL_RX 0x6
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-#define LED_VAL_TXRX 0x7 /* TX or RX */
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-#define LED_VAL_DUPLEXFULL 0x8
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-#define LED_VAL_COLLISION 0x9
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-#define LED_VAL_LINKON_ACTIVE 0xA /* Link on, activity blink */
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-#define LED_VAL_LINKON_RECV 0xB /* Link on, receive blink */
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-#define LED_VAL_DUPLEXFULL_COLLISION 0xC /* Duplex on, collision blink */
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-#define LED_VAL_BLINK 0xD
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-#define LED_VAL_ON 0xE
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-#define LED_VAL_OFF 0xF
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-
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-#define LED_LINK_SHIFT 12
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-#define LED_TXRX_SHIFT 8
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-#define LED_100TX_SHIFT 4
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-
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-/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
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-
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-/* Defines for PHY access routines */
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-
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-/* Define bit operation flags */
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-#define TRUEPHY_BIT_CLEAR 0
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-#define TRUEPHY_BIT_SET 1
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-#define TRUEPHY_BIT_READ 2
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-
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-/* Define read/write operation flags */
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-#ifndef TRUEPHY_READ
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-#define TRUEPHY_READ 0
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-#define TRUEPHY_WRITE 1
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-#define TRUEPHY_MASK 2
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-#endif
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-
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-/* Define master/slave configuration values */
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-#define TRUEPHY_CFG_SLAVE 0
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-#define TRUEPHY_CFG_MASTER 1
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-
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-/* Define MDI/MDI-X settings */
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-#define TRUEPHY_MDI 0
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-#define TRUEPHY_MDIX 1
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-#define TRUEPHY_AUTO_MDI_MDIX 2
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-
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-/* Define 10Base-T link polarities */
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-#define TRUEPHY_POLARITY_NORMAL 0
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-#define TRUEPHY_POLARITY_INVERTED 1
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-
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-/* Define auto-negotiation results */
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-#define TRUEPHY_ANEG_NOT_COMPLETE 0
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-#define TRUEPHY_ANEG_COMPLETE 1
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-#define TRUEPHY_ANEG_DISABLED 2
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-
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-/* Define duplex advertisement flags */
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-#define TRUEPHY_ADV_DUPLEX_NONE 0x00
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-#define TRUEPHY_ADV_DUPLEX_FULL 0x01
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-#define TRUEPHY_ADV_DUPLEX_HALF 0x02
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-#define TRUEPHY_ADV_DUPLEX_BOTH \
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- (TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF)
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-
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-#endif /* _ET1310_PHY_H_ */
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Mark Einon