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@@ -456,6 +456,9 @@ mclk_timing_set(struct nouveau_mem_exec_func *exec)
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if (info->ramcfg[2] & 0x02)
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unk718 |= 0x00000100;
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nv_wr32(dev, 0x100718, unk718);
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+
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+ if (info->ramcfg[2] & 0x10)
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+ nv_wr32(dev, 0x111100, 0x48000000); /*XXX*/
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}
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}
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@@ -498,15 +501,33 @@ prog_mem(struct drm_device *dev, struct nva3_pm_state *info)
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nv_mask(dev, 0x004168, 0x003f3141, ctrl);
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}
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+ if (info->ramcfg) {
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+ if (info->ramcfg[2] & 0x10) {
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+ nv_mask(dev, 0x111104, 0x00000600, 0x00000000);
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+ } else {
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+ nv_mask(dev, 0x111100, 0x40000000, 0x40000000);
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+ nv_mask(dev, 0x111104, 0x00000180, 0x00000000);
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+ }
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+ }
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if (info->rammap && !(info->rammap[4] & 0x02))
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nv_mask(dev, 0x100200, 0x00000800, 0x00000000);
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nv_wr32(dev, 0x611200, 0x00003300);
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+ if (!(info->ramcfg[2] & 0x10))
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+ nv_wr32(dev, 0x111100, 0x4c020000); /*XXX*/
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nouveau_mem_exec(&exec, info->perflvl);
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nv_wr32(dev, 0x611200, 0x00003330);
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if (info->rammap && (info->rammap[4] & 0x02))
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nv_mask(dev, 0x100200, 0x00000800, 0x00000800);
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+ if (info->ramcfg) {
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+ if (info->ramcfg[2] & 0x10) {
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+ nv_mask(dev, 0x111104, 0x00000180, 0x00000180);
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+ nv_mask(dev, 0x111100, 0x40000000, 0x00000000);
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+ } else {
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+ nv_mask(dev, 0x111104, 0x00000600, 0x00000600);
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+ }
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+ }
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if (info->mclk.pll) {
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nv_mask(dev, 0x004168, 0x00000001, 0x00000000);
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