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@@ -0,0 +1,412 @@
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+/*
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+ * Userspace Probes (UProbes) for x86
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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+ *
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+ * Copyright (C) IBM Corporation, 2008-2011
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+ * Authors:
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+ * Srikar Dronamraju
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+ * Jim Keniston
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/sched.h>
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+#include <linux/ptrace.h>
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+#include <linux/uprobes.h>
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+
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+#include <linux/kdebug.h>
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+#include <asm/insn.h>
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+
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+/* Post-execution fixups. */
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+
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+/* No fixup needed */
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+#define UPROBES_FIX_NONE 0x0
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+/* Adjust IP back to vicinity of actual insn */
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+#define UPROBES_FIX_IP 0x1
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+/* Adjust the return address of a call insn */
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+#define UPROBES_FIX_CALL 0x2
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+
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+#define UPROBES_FIX_RIP_AX 0x8000
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+#define UPROBES_FIX_RIP_CX 0x4000
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+
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+/* Adaptations for mhiramat x86 decoder v14. */
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+#define OPCODE1(insn) ((insn)->opcode.bytes[0])
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+#define OPCODE2(insn) ((insn)->opcode.bytes[1])
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+#define OPCODE3(insn) ((insn)->opcode.bytes[2])
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+#define MODRM_REG(insn) X86_MODRM_REG(insn->modrm.value)
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+
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+#define W(row, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, ba, bb, bc, bd, be, bf)\
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+ (((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \
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+ (b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) | \
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+ (b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) | \
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+ (bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf)) \
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+ << (row % 32))
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+
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+#ifdef CONFIG_X86_64
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+static volatile u32 good_insns_64[256 / 32] = {
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+ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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+ /* ---------------------------------------------- */
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+ W(0x00, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) | /* 00 */
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+ W(0x10, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 10 */
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+ W(0x20, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) | /* 20 */
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+ W(0x30, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 30 */
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+ W(0x40, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) | /* 40 */
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+ W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
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+ W(0x60, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
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+ W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
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+ W(0x80, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
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+ W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
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+ W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
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+ W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
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+ W(0xc0, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
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+ W(0xd0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
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+ W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */
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+ W(0xf0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */
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+ /* ---------------------------------------------- */
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+ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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+};
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+#endif
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+
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+/* Good-instruction tables for 32-bit apps */
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+
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+static volatile u32 good_insns_32[256 / 32] = {
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+ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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+ /* ---------------------------------------------- */
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+ W(0x00, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) | /* 00 */
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+ W(0x10, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 10 */
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+ W(0x20, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1) | /* 20 */
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+ W(0x30, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1) , /* 30 */
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+ W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
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+ W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
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+ W(0x60, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
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+ W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
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+ W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
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+ W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
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+ W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
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+ W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
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+ W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
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+ W(0xd0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
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+ W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */
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+ W(0xf0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */
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+ /* ---------------------------------------------- */
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+ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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+};
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+
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+/* Using this for both 64-bit and 32-bit apps */
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+static volatile u32 good_2byte_insns[256 / 32] = {
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+ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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+ /* ---------------------------------------------- */
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+ W(0x00, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1) | /* 00 */
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+ W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1) , /* 10 */
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+ W(0x20, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */
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+ W(0x30, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) , /* 30 */
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+ W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
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+ W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
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+ W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */
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+ W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1) , /* 70 */
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+ W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
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+ W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
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+ W(0xa0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */
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+ W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
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+ W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */
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+ W(0xd0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
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+ W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */
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+ W(0xf0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0) /* f0 */
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+ /* ---------------------------------------------- */
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+ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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+};
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+
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+#undef W
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+
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+/*
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+ * opcodes we'll probably never support:
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+ * 6c-6d, e4-e5, ec-ed - in
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+ * 6e-6f, e6-e7, ee-ef - out
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+ * cc, cd - int3, int
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+ * cf - iret
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+ * d6 - illegal instruction
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+ * f1 - int1/icebp
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+ * f4 - hlt
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+ * fa, fb - cli, sti
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+ * 0f - lar, lsl, syscall, clts, sysret, sysenter, sysexit, invd, wbinvd, ud2
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+ *
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+ * invalid opcodes in 64-bit mode:
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+ * 06, 0e, 16, 1e, 27, 2f, 37, 3f, 60-62, 82, c4-c5, d4-d5
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+ *
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+ * 63 - we support this opcode in x86_64 but not in i386.
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+ *
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+ * opcodes we may need to refine support for:
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+ * 0f - 2-byte instructions: For many of these instructions, the validity
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+ * depends on the prefix and/or the reg field. On such instructions, we
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+ * just consider the opcode combination valid if it corresponds to any
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+ * valid instruction.
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+ * 8f - Group 1 - only reg = 0 is OK
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+ * c6-c7 - Group 11 - only reg = 0 is OK
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+ * d9-df - fpu insns with some illegal encodings
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+ * f2, f3 - repnz, repz prefixes. These are also the first byte for
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+ * certain floating-point instructions, such as addsd.
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+ * fe - Group 4 - only reg = 0 or 1 is OK
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+ * ff - Group 5 - only reg = 0-6 is OK
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+ *
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+ * others -- Do we need to support these?
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+ * 0f - (floating-point?) prefetch instructions
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+ * 07, 17, 1f - pop es, pop ss, pop ds
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+ * 26, 2e, 36, 3e - es:, cs:, ss:, ds: segment prefixes --
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+ * but 64 and 65 (fs: and gs:) seem to be used, so we support them
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+ * 67 - addr16 prefix
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+ * ce - into
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+ * f0 - lock prefix
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+ */
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+
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+/*
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+ * TODO:
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+ * - Where necessary, examine the modrm byte and allow only valid instructions
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+ * in the different Groups and fpu instructions.
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+ */
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+
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+static bool is_prefix_bad(struct insn *insn)
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+{
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+ int i;
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+
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+ for (i = 0; i < insn->prefixes.nbytes; i++) {
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+ switch (insn->prefixes.bytes[i]) {
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+ case 0x26: /*INAT_PFX_ES */
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+ case 0x2E: /*INAT_PFX_CS */
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+ case 0x36: /*INAT_PFX_DS */
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+ case 0x3E: /*INAT_PFX_SS */
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+ case 0xF0: /*INAT_PFX_LOCK */
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+ return true;
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+ }
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+ }
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+ return false;
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+}
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+
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+static int validate_insn_32bits(struct uprobe *uprobe, struct insn *insn)
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+{
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+ insn_init(insn, uprobe->insn, false);
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+
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+ /* Skip good instruction prefixes; reject "bad" ones. */
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+ insn_get_opcode(insn);
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+ if (is_prefix_bad(insn))
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+ return -ENOTSUPP;
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+ if (test_bit(OPCODE1(insn), (unsigned long *)good_insns_32))
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+ return 0;
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+ if (insn->opcode.nbytes == 2) {
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+ if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns))
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+ return 0;
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+ }
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+ return -ENOTSUPP;
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+}
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+
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+/*
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+ * Figure out which fixups post_xol() will need to perform, and annotate
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+ * uprobe->arch_info.fixups accordingly. To start with,
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+ * uprobe->arch_info.fixups is either zero or it reflects rip-related
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+ * fixups.
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+ */
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+static void prepare_fixups(struct uprobe *uprobe, struct insn *insn)
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+{
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+ bool fix_ip = true, fix_call = false; /* defaults */
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+ int reg;
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+
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+ insn_get_opcode(insn); /* should be a nop */
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+
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+ switch (OPCODE1(insn)) {
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+ case 0xc3: /* ret/lret */
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+ case 0xcb:
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+ case 0xc2:
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+ case 0xca:
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+ /* ip is correct */
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+ fix_ip = false;
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+ break;
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+ case 0xe8: /* call relative - Fix return addr */
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+ fix_call = true;
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+ break;
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+ case 0x9a: /* call absolute - Fix return addr, not ip */
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+ fix_call = true;
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+ fix_ip = false;
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+ break;
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+ case 0xff:
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+ insn_get_modrm(insn);
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+ reg = MODRM_REG(insn);
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+ if (reg == 2 || reg == 3) {
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+ /* call or lcall, indirect */
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+ /* Fix return addr; ip is correct. */
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+ fix_call = true;
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+ fix_ip = false;
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+ } else if (reg == 4 || reg == 5) {
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+ /* jmp or ljmp, indirect */
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+ /* ip is correct. */
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+ fix_ip = false;
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+ }
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+ break;
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+ case 0xea: /* jmp absolute -- ip is correct */
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+ fix_ip = false;
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+ break;
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+ default:
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+ break;
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+ }
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+ if (fix_ip)
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+ uprobe->arch_info.fixups |= UPROBES_FIX_IP;
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+ if (fix_call)
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+ uprobe->arch_info.fixups |= UPROBES_FIX_CALL;
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+}
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+
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+#ifdef CONFIG_X86_64
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+/*
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+ * If uprobe->insn doesn't use rip-relative addressing, return
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+ * immediately. Otherwise, rewrite the instruction so that it accesses
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+ * its memory operand indirectly through a scratch register. Set
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+ * uprobe->arch_info.fixups and uprobe->arch_info.rip_rela_target_address
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+ * accordingly. (The contents of the scratch register will be saved
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+ * before we single-step the modified instruction, and restored
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+ * afterward.)
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+ *
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+ * We do this because a rip-relative instruction can access only a
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+ * relatively small area (+/- 2 GB from the instruction), and the XOL
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+ * area typically lies beyond that area. At least for instructions
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+ * that store to memory, we can't execute the original instruction
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+ * and "fix things up" later, because the misdirected store could be
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+ * disastrous.
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+ *
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+ * Some useful facts about rip-relative instructions:
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+ * - There's always a modrm byte.
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+ * - There's never a SIB byte.
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+ * - The displacement is always 4 bytes.
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+ */
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+static void handle_riprel_insn(struct mm_struct *mm, struct uprobe *uprobe,
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+ struct insn *insn)
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+{
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+ u8 *cursor;
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+ u8 reg;
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+
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+ if (mm->context.ia32_compat)
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+ return;
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+
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+ uprobe->arch_info.rip_rela_target_address = 0x0;
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+ if (!insn_rip_relative(insn))
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+ return;
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+
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+ /*
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+ * insn_rip_relative() would have decoded rex_prefix, modrm.
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+ * Clear REX.b bit (extension of MODRM.rm field):
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+ * we want to encode rax/rcx, not r8/r9.
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+ */
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+ if (insn->rex_prefix.nbytes) {
|
|
|
+ cursor = uprobe->insn + insn_offset_rex_prefix(insn);
|
|
|
+ *cursor &= 0xfe; /* Clearing REX.B bit */
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Point cursor at the modrm byte. The next 4 bytes are the
|
|
|
+ * displacement. Beyond the displacement, for some instructions,
|
|
|
+ * is the immediate operand.
|
|
|
+ */
|
|
|
+ cursor = uprobe->insn + insn_offset_modrm(insn);
|
|
|
+ insn_get_length(insn);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Convert from rip-relative addressing to indirect addressing
|
|
|
+ * via a scratch register. Change the r/m field from 0x5 (%rip)
|
|
|
+ * to 0x0 (%rax) or 0x1 (%rcx), and squeeze out the offset field.
|
|
|
+ */
|
|
|
+ reg = MODRM_REG(insn);
|
|
|
+ if (reg == 0) {
|
|
|
+ /*
|
|
|
+ * The register operand (if any) is either the A register
|
|
|
+ * (%rax, %eax, etc.) or (if the 0x4 bit is set in the
|
|
|
+ * REX prefix) %r8. In any case, we know the C register
|
|
|
+ * is NOT the register operand, so we use %rcx (register
|
|
|
+ * #1) for the scratch register.
|
|
|
+ */
|
|
|
+ uprobe->arch_info.fixups = UPROBES_FIX_RIP_CX;
|
|
|
+ /* Change modrm from 00 000 101 to 00 000 001. */
|
|
|
+ *cursor = 0x1;
|
|
|
+ } else {
|
|
|
+ /* Use %rax (register #0) for the scratch register. */
|
|
|
+ uprobe->arch_info.fixups = UPROBES_FIX_RIP_AX;
|
|
|
+ /* Change modrm from 00 xxx 101 to 00 xxx 000 */
|
|
|
+ *cursor = (reg << 3);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Target address = address of next instruction + (signed) offset */
|
|
|
+ uprobe->arch_info.rip_rela_target_address = (long)insn->length
|
|
|
+ + insn->displacement.value;
|
|
|
+ /* Displacement field is gone; slide immediate field (if any) over. */
|
|
|
+ if (insn->immediate.nbytes) {
|
|
|
+ cursor++;
|
|
|
+ memmove(cursor, cursor + insn->displacement.nbytes,
|
|
|
+ insn->immediate.nbytes);
|
|
|
+ }
|
|
|
+ return;
|
|
|
+}
|
|
|
+
|
|
|
+static int validate_insn_64bits(struct uprobe *uprobe, struct insn *insn)
|
|
|
+{
|
|
|
+ insn_init(insn, uprobe->insn, true);
|
|
|
+
|
|
|
+ /* Skip good instruction prefixes; reject "bad" ones. */
|
|
|
+ insn_get_opcode(insn);
|
|
|
+ if (is_prefix_bad(insn))
|
|
|
+ return -ENOTSUPP;
|
|
|
+ if (test_bit(OPCODE1(insn), (unsigned long *)good_insns_64))
|
|
|
+ return 0;
|
|
|
+ if (insn->opcode.nbytes == 2) {
|
|
|
+ if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns))
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+ return -ENOTSUPP;
|
|
|
+}
|
|
|
+
|
|
|
+static int validate_insn_bits(struct mm_struct *mm, struct uprobe *uprobe,
|
|
|
+ struct insn *insn)
|
|
|
+{
|
|
|
+ if (mm->context.ia32_compat)
|
|
|
+ return validate_insn_32bits(uprobe, insn);
|
|
|
+ return validate_insn_64bits(uprobe, insn);
|
|
|
+}
|
|
|
+#else
|
|
|
+static void handle_riprel_insn(struct mm_struct *mm, struct uprobe *uprobe,
|
|
|
+ struct insn *insn)
|
|
|
+{
|
|
|
+ return;
|
|
|
+}
|
|
|
+
|
|
|
+static int validate_insn_bits(struct mm_struct *mm, struct uprobe *uprobe,
|
|
|
+ struct insn *insn)
|
|
|
+{
|
|
|
+ return validate_insn_32bits(uprobe, insn);
|
|
|
+}
|
|
|
+#endif /* CONFIG_X86_64 */
|
|
|
+
|
|
|
+/**
|
|
|
+ * analyze_insn - instruction analysis including validity and fixups.
|
|
|
+ * @mm: the probed address space.
|
|
|
+ * @uprobe: the probepoint information.
|
|
|
+ * Return 0 on success or a -ve number on error.
|
|
|
+ */
|
|
|
+int analyze_insn(struct mm_struct *mm, struct uprobe *uprobe)
|
|
|
+{
|
|
|
+ int ret;
|
|
|
+ struct insn insn;
|
|
|
+
|
|
|
+ uprobe->arch_info.fixups = 0;
|
|
|
+ ret = validate_insn_bits(mm, uprobe, &insn);
|
|
|
+ if (ret != 0)
|
|
|
+ return ret;
|
|
|
+ handle_riprel_insn(mm, uprobe, &insn);
|
|
|
+ prepare_fixups(uprobe, &insn);
|
|
|
+ return 0;
|
|
|
+}
|