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@@ -0,0 +1,1490 @@
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+/*
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+ * drivers/ata/sata_fsl.c
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+ *
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+ * Freescale 3.0Gbps SATA device driver
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+ *
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+ * Author: Ashish Kalra <ashish.kalra@freescale.com>
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+ * Li Yang <leoli@freescale.com>
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+ *
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+ * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+
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+#include <scsi/scsi_host.h>
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+#include <scsi/scsi_cmnd.h>
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+#include <linux/libata.h>
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+#include <asm/io.h>
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+#include <linux/of_platform.h>
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+
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+/* Controller information */
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+enum {
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+ SATA_FSL_QUEUE_DEPTH = 16,
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+ SATA_FSL_MAX_PRD = 63,
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+ SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
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+ SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
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+
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+ SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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+ ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
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+ ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY),
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+
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+ SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
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+ SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
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+ SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
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+
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+ /*
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+ * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
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+ * chained indirect PRDEs upto a max count of 63.
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+ * We are allocating an array of 63 PRDEs contigiously, but PRDE#15 will
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+ * be setup as an indirect descriptor, pointing to it's next
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+ * (contigious) PRDE. Though chained indirect PRDE arrays are
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+ * supported,it will be more efficient to use a direct PRDT and
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+ * a single chain/link to indirect PRDE array/PRDT.
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+ */
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+
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+ SATA_FSL_CMD_DESC_CFIS_SZ = 32,
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+ SATA_FSL_CMD_DESC_SFIS_SZ = 32,
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+ SATA_FSL_CMD_DESC_ACMD_SZ = 16,
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+ SATA_FSL_CMD_DESC_RSRVD = 16,
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+
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+ SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
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+ SATA_FSL_CMD_DESC_SFIS_SZ +
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+ SATA_FSL_CMD_DESC_ACMD_SZ +
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+ SATA_FSL_CMD_DESC_RSRVD +
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+ SATA_FSL_MAX_PRD * 16),
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+
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+ SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
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+ (SATA_FSL_CMD_DESC_CFIS_SZ +
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+ SATA_FSL_CMD_DESC_SFIS_SZ +
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+ SATA_FSL_CMD_DESC_ACMD_SZ +
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+ SATA_FSL_CMD_DESC_RSRVD),
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+
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+ SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
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+ SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
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+ SATA_FSL_CMD_DESC_AR_SZ),
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+
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+ /*
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+ * MPC8315 has two SATA controllers, SATA1 & SATA2
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+ * (one port per controller)
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+ * MPC837x has 2/4 controllers, one port per controller
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+ */
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+
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+ SATA_FSL_MAX_PORTS = 1,
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+
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+ SATA_FSL_IRQ_FLAG = IRQF_SHARED,
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+};
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+
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+/*
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+* Host Controller command register set - per port
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+*/
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+enum {
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+ CQ = 0,
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+ CA = 8,
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+ CC = 0x10,
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+ CE = 0x18,
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+ DE = 0x20,
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+ CHBA = 0x24,
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+ HSTATUS = 0x28,
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+ HCONTROL = 0x2C,
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+ CQPMP = 0x30,
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+ SIGNATURE = 0x34,
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+ ICC = 0x38,
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+
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+ /*
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+ * Host Status Register (HStatus) bitdefs
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+ */
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+ ONLINE = (1 << 31),
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+ GOING_OFFLINE = (1 << 30),
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+ BIST_ERR = (1 << 29),
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+
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+ FATAL_ERR_HC_MASTER_ERR = (1 << 18),
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+ FATAL_ERR_PARITY_ERR_TX = (1 << 17),
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+ FATAL_ERR_PARITY_ERR_RX = (1 << 16),
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+ FATAL_ERR_DATA_UNDERRUN = (1 << 13),
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+ FATAL_ERR_DATA_OVERRUN = (1 << 12),
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+ FATAL_ERR_CRC_ERR_TX = (1 << 11),
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+ FATAL_ERR_CRC_ERR_RX = (1 << 10),
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+ FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
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+ FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
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+
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+ FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
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+ FATAL_ERR_PARITY_ERR_TX |
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+ FATAL_ERR_PARITY_ERR_RX |
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+ FATAL_ERR_DATA_UNDERRUN |
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+ FATAL_ERR_DATA_OVERRUN |
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+ FATAL_ERR_CRC_ERR_TX |
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+ FATAL_ERR_CRC_ERR_RX |
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+ FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
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+
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+ INT_ON_FATAL_ERR = (1 << 5),
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+ INT_ON_PHYRDY_CHG = (1 << 4),
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+
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+ INT_ON_SIGNATURE_UPDATE = (1 << 3),
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+ INT_ON_SNOTIFY_UPDATE = (1 << 2),
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+ INT_ON_SINGL_DEVICE_ERR = (1 << 1),
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+ INT_ON_CMD_COMPLETE = 1,
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+
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+ INT_ON_ERROR = INT_ON_FATAL_ERR |
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+ INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
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+
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+ /*
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+ * Host Control Register (HControl) bitdefs
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+ */
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+ HCONTROL_ONLINE_PHY_RST = (1 << 31),
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+ HCONTROL_FORCE_OFFLINE = (1 << 30),
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+ HCONTROL_PARITY_PROT_MOD = (1 << 14),
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+ HCONTROL_DPATH_PARITY = (1 << 12),
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+ HCONTROL_SNOOP_ENABLE = (1 << 10),
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+ HCONTROL_PMP_ATTACHED = (1 << 9),
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+ HCONTROL_COPYOUT_STATFIS = (1 << 8),
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+ IE_ON_FATAL_ERR = (1 << 5),
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+ IE_ON_PHYRDY_CHG = (1 << 4),
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+ IE_ON_SIGNATURE_UPDATE = (1 << 3),
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+ IE_ON_SNOTIFY_UPDATE = (1 << 2),
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+ IE_ON_SINGL_DEVICE_ERR = (1 << 1),
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+ IE_ON_CMD_COMPLETE = 1,
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+
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+ DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
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+ IE_ON_SIGNATURE_UPDATE |
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+ IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
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+
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+ EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
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+ DATA_SNOOP_ENABLE = (1 << 22),
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+};
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+
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+/*
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+ * SATA Superset Registers
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+ */
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+enum {
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+ SSTATUS = 0,
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+ SERROR = 4,
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+ SCONTROL = 8,
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+ SNOTIFY = 0xC,
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+};
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+
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+/*
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+ * Control Status Register Set
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+ */
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+enum {
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+ TRANSCFG = 0,
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+ TRANSSTATUS = 4,
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+ LINKCFG = 8,
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+ LINKCFG1 = 0xC,
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+ LINKCFG2 = 0x10,
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+ LINKSTATUS = 0x14,
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+ LINKSTATUS1 = 0x18,
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+ PHYCTRLCFG = 0x1C,
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+ COMMANDSTAT = 0x20,
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+};
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+
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+/* PHY (link-layer) configuration control */
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+enum {
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+ PHY_BIST_ENABLE = 0x01,
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+};
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+
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+/*
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+ * Command Header Table entry, i.e, command slot
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+ * 4 Dwords per command slot, command header size == 64 Dwords.
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+ */
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+struct cmdhdr_tbl_entry {
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+ u32 cda;
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+ u32 prde_fis_len;
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+ u32 ttl;
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+ u32 desc_info;
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+};
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+
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+/*
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+ * Description information bitdefs
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+ */
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+enum {
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+ VENDOR_SPECIFIC_BIST = (1 << 10),
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+ CMD_DESC_SNOOP_ENABLE = (1 << 9),
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+ FPDMA_QUEUED_CMD = (1 << 8),
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+ SRST_CMD = (1 << 7),
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+ BIST = (1 << 6),
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+ ATAPI_CMD = (1 << 5),
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+};
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+
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+/*
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+ * Command Descriptor
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+ */
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+struct command_desc {
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+ u8 cfis[8 * 4];
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+ u8 sfis[8 * 4];
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+ u8 acmd[4 * 4];
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+ u8 fill[4 * 4];
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+ u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
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+ u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
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+};
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+
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+/*
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+ * Physical region table descriptor(PRD)
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+ */
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+
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+struct prde {
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+ u32 dba;
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+ u8 fill[2 * 4];
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+ u32 ddc_and_ext;
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+};
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+
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+/*
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+ * ata_port private data
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+ * This is our per-port instance data.
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+ */
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+struct sata_fsl_port_priv {
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+ struct cmdhdr_tbl_entry *cmdslot;
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+ dma_addr_t cmdslot_paddr;
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+ struct command_desc *cmdentry;
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+ dma_addr_t cmdentry_paddr;
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+
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+ /*
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+ * SATA FSL controller has a Status FIS which should contain the
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+ * received D2H FIS & taskfile registers. This SFIS is present in
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+ * the command descriptor, and to have a ready reference to it,
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+ * we are caching it here, quite similar to what is done in H/W on
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+ * AHCI compliant devices by copying taskfile fields to a 32-bit
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+ * register.
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+ */
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+
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+ struct ata_taskfile tf;
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+};
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+
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+/*
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+ * ata_port->host_set private data
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+ */
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+struct sata_fsl_host_priv {
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+ void __iomem *hcr_base;
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+ void __iomem *ssr_base;
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+ void __iomem *csr_base;
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+};
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+
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+static inline unsigned int sata_fsl_tag(unsigned int tag,
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+ void __iomem * hcr_base)
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+{
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+ /* We let libATA core do actual (queue) tag allocation */
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+
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+ /* all non NCQ/queued commands should have tag#0 */
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+ if (ata_tag_internal(tag)) {
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+ DPRINTK("mapping internal cmds to tag#0\n");
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+ return 0;
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+ }
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+
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+ if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
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+ DPRINTK("tag %d invalid : out of range\n", tag);
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+ return 0;
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+ }
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+
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+ if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
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+ DPRINTK("tag %d invalid : in use!!\n", tag);
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+ return 0;
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+ }
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+
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+ return tag;
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+}
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+
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+static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
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+ unsigned int tag, u32 desc_info,
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+ u32 data_xfer_len, u8 num_prde,
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+ u8 fis_len)
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+{
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+ dma_addr_t cmd_descriptor_address;
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+
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+ cmd_descriptor_address = pp->cmdentry_paddr +
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+ tag * SATA_FSL_CMD_DESC_SIZE;
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+
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+ /* NOTE: both data_xfer_len & fis_len are Dword counts */
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+
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+ pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
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+ pp->cmdslot[tag].prde_fis_len =
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+ cpu_to_le32((num_prde << 16) | (fis_len << 2));
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+ pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
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+ pp->cmdslot[tag].desc_info = cpu_to_le32((desc_info | (tag & 0x1F)));
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+
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+ VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
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+ pp->cmdslot[tag].cda,
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+ pp->cmdslot[tag].prde_fis_len,
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+ pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
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+
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+}
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+
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+static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
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+ u32 * ttl, dma_addr_t cmd_desc_paddr)
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+{
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+ struct scatterlist *sg;
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+ unsigned int num_prde = 0;
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+ u32 ttl_dwords = 0;
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+
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+ /*
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+ * NOTE : direct & indirect prdt's are contigiously allocated
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+ */
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+ struct prde *prd = (struct prde *)&((struct command_desc *)
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+ cmd_desc)->prdt;
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+
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+ struct prde *prd_ptr_to_indirect_ext = NULL;
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+ unsigned indirect_ext_segment_sz = 0;
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+ dma_addr_t indirect_ext_segment_paddr;
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+
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+ VPRINTK("SATA FSL : cd = 0x%x, prd = 0x%x\n", cmd_desc, prd);
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+
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+ indirect_ext_segment_paddr = cmd_desc_paddr +
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+ SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
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+
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+ ata_for_each_sg(sg, qc) {
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+ dma_addr_t sg_addr = sg_dma_address(sg);
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+ u32 sg_len = sg_dma_len(sg);
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+
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+ VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%x, sg_len = %d\n",
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+ sg_addr, sg_len);
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+
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+ /* warn if each s/g element is not dword aligned */
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+ if (sg_addr & 0x03)
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+ ata_port_printk(qc->ap, KERN_ERR,
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+ "s/g addr unaligned : 0x%x\n", sg_addr);
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+ if (sg_len & 0x03)
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+ ata_port_printk(qc->ap, KERN_ERR,
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+ "s/g len unaligned : 0x%x\n", sg_len);
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+
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+ if ((num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1)) &&
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+ !ata_sg_is_last(sg, qc)) {
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+ VPRINTK("setting indirect prde\n");
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+ prd_ptr_to_indirect_ext = prd;
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+ prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
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+ indirect_ext_segment_sz = 0;
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+ ++prd;
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+ ++num_prde;
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+ }
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+
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+ ttl_dwords += sg_len;
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+ prd->dba = cpu_to_le32(sg_addr);
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+ prd->ddc_and_ext =
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+ cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03));
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+
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+ VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
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+ ttl_dwords, prd->dba, prd->ddc_and_ext);
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+
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+ ++num_prde;
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+ ++prd;
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+ if (prd_ptr_to_indirect_ext)
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+ indirect_ext_segment_sz += sg_len;
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+ }
|
|
|
+
|
|
|
+ if (prd_ptr_to_indirect_ext) {
|
|
|
+ /* set indirect extension flag along with indirect ext. size */
|
|
|
+ prd_ptr_to_indirect_ext->ddc_and_ext =
|
|
|
+ cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
|
|
|
+ DATA_SNOOP_ENABLE |
|
|
|
+ (indirect_ext_segment_sz & ~0x03)));
|
|
|
+ }
|
|
|
+
|
|
|
+ *ttl = ttl_dwords;
|
|
|
+ return num_prde;
|
|
|
+}
|
|
|
+
|
|
|
+static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
|
|
|
+{
|
|
|
+ struct ata_port *ap = qc->ap;
|
|
|
+ struct sata_fsl_port_priv *pp = ap->private_data;
|
|
|
+ struct sata_fsl_host_priv *host_priv = ap->host->private_data;
|
|
|
+ void __iomem *hcr_base = host_priv->hcr_base;
|
|
|
+ unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
|
|
|
+ struct command_desc *cd;
|
|
|
+ u32 desc_info = CMD_DESC_SNOOP_ENABLE;
|
|
|
+ u32 num_prde = 0;
|
|
|
+ u32 ttl_dwords = 0;
|
|
|
+ dma_addr_t cd_paddr;
|
|
|
+
|
|
|
+ cd = (struct command_desc *)pp->cmdentry + tag;
|
|
|
+ cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
|
|
|
+
|
|
|
+ ata_tf_to_fis(&qc->tf, 0, 1, (u8 *) & cd->cfis);
|
|
|
+
|
|
|
+ VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
|
|
|
+ cd->cfis[0], cd->cfis[1], cd->cfis[2]);
|
|
|
+
|
|
|
+ if (qc->tf.protocol == ATA_PROT_NCQ) {
|
|
|
+ VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
|
|
|
+ cd->cfis[3], cd->cfis[11]);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
|
|
|
+ if (is_atapi_taskfile(&qc->tf)) {
|
|
|
+ desc_info |= ATAPI_CMD;
|
|
|
+ memset((void *)&cd->acmd, 0, 32);
|
|
|
+ memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (qc->flags & ATA_QCFLAG_DMAMAP)
|
|
|
+ num_prde = sata_fsl_fill_sg(qc, (void *)cd,
|
|
|
+ &ttl_dwords, cd_paddr);
|
|
|
+
|
|
|
+ if (qc->tf.protocol == ATA_PROT_NCQ)
|
|
|
+ desc_info |= FPDMA_QUEUED_CMD;
|
|
|
+
|
|
|
+ sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
|
|
|
+ num_prde, 5);
|
|
|
+
|
|
|
+ VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
|
|
|
+ desc_info, ttl_dwords, num_prde);
|
|
|
+}
|
|
|
+
|
|
|
+static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
|
|
|
+{
|
|
|
+ struct ata_port *ap = qc->ap;
|
|
|
+ struct sata_fsl_host_priv *host_priv = ap->host->private_data;
|
|
|
+ void __iomem *hcr_base = host_priv->hcr_base;
|
|
|
+ unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
|
|
|
+
|
|
|
+ VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
|
|
|
+ ioread32(CQ + hcr_base),
|
|
|
+ ioread32(CA + hcr_base),
|
|
|
+ ioread32(CE + hcr_base), ioread32(CC + hcr_base));
|
|
|
+
|
|
|
+ /* Simply queue command to the controller/device */
|
|
|
+ iowrite32(1 << tag, CQ + hcr_base);
|
|
|
+
|
|
|
+ VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
|
|
|
+ tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
|
|
|
+
|
|
|
+ VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
|
|
|
+ ioread32(CE + hcr_base),
|
|
|
+ ioread32(DE + hcr_base),
|
|
|
+ ioread32(CC + hcr_base), ioread32(COMMANDSTAT + csr_base));
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int sata_fsl_scr_write(struct ata_port *ap, unsigned int sc_reg_in,
|
|
|
+ u32 val)
|
|
|
+{
|
|
|
+ struct sata_fsl_host_priv *host_priv = ap->host->private_data;
|
|
|
+ void __iomem *ssr_base = host_priv->ssr_base;
|
|
|
+ unsigned int sc_reg;
|
|
|
+
|
|
|
+ switch (sc_reg_in) {
|
|
|
+ case SCR_STATUS:
|
|
|
+ sc_reg = 0;
|
|
|
+ break;
|
|
|
+ case SCR_ERROR:
|
|
|
+ sc_reg = 1;
|
|
|
+ break;
|
|
|
+ case SCR_CONTROL:
|
|
|
+ sc_reg = 2;
|
|
|
+ break;
|
|
|
+ case SCR_ACTIVE:
|
|
|
+ sc_reg = 3;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
|
|
|
+
|
|
|
+ iowrite32(val, (void __iomem *)ssr_base + (sc_reg * 4));
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int sata_fsl_scr_read(struct ata_port *ap, unsigned int sc_reg_in,
|
|
|
+ u32 *val)
|
|
|
+{
|
|
|
+ struct sata_fsl_host_priv *host_priv = ap->host->private_data;
|
|
|
+ void __iomem *ssr_base = host_priv->ssr_base;
|
|
|
+ unsigned int sc_reg;
|
|
|
+
|
|
|
+ switch (sc_reg_in) {
|
|
|
+ case SCR_STATUS:
|
|
|
+ sc_reg = 0;
|
|
|
+ break;
|
|
|
+ case SCR_ERROR:
|
|
|
+ sc_reg = 1;
|
|
|
+ break;
|
|
|
+ case SCR_CONTROL:
|
|
|
+ sc_reg = 2;
|
|
|
+ break;
|
|
|
+ case SCR_ACTIVE:
|
|
|
+ sc_reg = 3;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
|
|
|
+
|
|
|
+ *val = ioread32((void __iomem *)ssr_base + (sc_reg * 4));
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void sata_fsl_freeze(struct ata_port *ap)
|
|
|
+{
|
|
|
+ struct sata_fsl_host_priv *host_priv = ap->host->private_data;
|
|
|
+ void __iomem *hcr_base = host_priv->hcr_base;
|
|
|
+ u32 temp;
|
|
|
+
|
|
|
+ VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
|
|
|
+ ioread32(CQ + hcr_base),
|
|
|
+ ioread32(CA + hcr_base),
|
|
|
+ ioread32(CE + hcr_base), ioread32(DE + hcr_base));
|
|
|
+ VPRINTK("CmdStat = 0x%x\n", ioread32(csr_base + COMMANDSTAT));
|
|
|
+
|
|
|
+ /* disable interrupts on the controller/port */
|
|
|
+ temp = ioread32(hcr_base + HCONTROL);
|
|
|
+ iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
|
|
|
+
|
|
|
+ VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
|
|
|
+ ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
|
|
|
+}
|
|
|
+
|
|
|
+static void sata_fsl_thaw(struct ata_port *ap)
|
|
|
+{
|
|
|
+ struct sata_fsl_host_priv *host_priv = ap->host->private_data;
|
|
|
+ void __iomem *hcr_base = host_priv->hcr_base;
|
|
|
+ u32 temp;
|
|
|
+
|
|
|
+ /* ack. any pending IRQs for this controller/port */
|
|
|
+ temp = ioread32(hcr_base + HSTATUS);
|
|
|
+
|
|
|
+ VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
|
|
|
+
|
|
|
+ if (temp & 0x3F)
|
|
|
+ iowrite32((temp & 0x3F), hcr_base + HSTATUS);
|
|
|
+
|
|
|
+ /* enable interrupts on the controller/port */
|
|
|
+ temp = ioread32(hcr_base + HCONTROL);
|
|
|
+ iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
|
|
|
+
|
|
|
+ VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
|
|
|
+ ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * NOTE : 1st D2H FIS from device does not update sfis in command descriptor.
|
|
|
+ */
|
|
|
+static inline void sata_fsl_cache_taskfile_from_d2h_fis(struct ata_queued_cmd
|
|
|
+ *qc,
|
|
|
+ struct ata_port *ap)
|
|
|
+{
|
|
|
+ struct sata_fsl_port_priv *pp = ap->private_data;
|
|
|
+ u8 fis[6 * 4];
|
|
|
+ struct sata_fsl_host_priv *host_priv = ap->host->private_data;
|
|
|
+ void __iomem *hcr_base = host_priv->hcr_base;
|
|
|
+ unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
|
|
|
+ struct command_desc *cd;
|
|
|
+
|
|
|
+ cd = pp->cmdentry + tag;
|
|
|
+
|
|
|
+ memcpy(fis, &cd->sfis, 6 * 4); /* should we use memcpy_from_io() */
|
|
|
+ ata_tf_from_fis(fis, &pp->tf);
|
|
|
+}
|
|
|
+
|
|
|
+static u8 sata_fsl_check_status(struct ata_port *ap)
|
|
|
+{
|
|
|
+ struct sata_fsl_port_priv *pp = ap->private_data;
|
|
|
+
|
|
|
+ return pp->tf.command;
|
|
|
+}
|
|
|
+
|
|
|
+static void sata_fsl_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
|
|
|
+{
|
|
|
+ struct sata_fsl_port_priv *pp = ap->private_data;
|
|
|
+
|
|
|
+ *tf = pp->tf;
|
|
|
+}
|
|
|
+
|
|
|
+static int sata_fsl_port_start(struct ata_port *ap)
|
|
|
+{
|
|
|
+ struct device *dev = ap->host->dev;
|
|
|
+ struct sata_fsl_port_priv *pp;
|
|
|
+ int retval;
|
|
|
+ void *mem;
|
|
|
+ dma_addr_t mem_dma;
|
|
|
+ struct sata_fsl_host_priv *host_priv = ap->host->private_data;
|
|
|
+ void __iomem *hcr_base = host_priv->hcr_base;
|
|
|
+ u32 temp;
|
|
|
+
|
|
|
+ pp = kzalloc(sizeof(*pp), GFP_KERNEL);
|
|
|
+ if (!pp)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * allocate per command dma alignment pad buffer, which is used
|
|
|
+ * internally by libATA to ensure that all transfers ending on
|
|
|
+ * unaligned boundaries are padded, to align on Dword boundaries
|
|
|
+ */
|
|
|
+ retval = ata_pad_alloc(ap, dev);
|
|
|
+ if (retval) {
|
|
|
+ kfree(pp);
|
|
|
+ return retval;
|
|
|
+ }
|
|
|
+
|
|
|
+ mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
|
|
|
+ GFP_KERNEL);
|
|
|
+ if (!mem) {
|
|
|
+ ata_pad_free(ap, dev);
|
|
|
+ kfree(pp);
|
|
|
+ return -ENOMEM;
|
|
|
+ }
|
|
|
+ memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ);
|
|
|
+
|
|
|
+ pp->cmdslot = mem;
|
|
|
+ pp->cmdslot_paddr = mem_dma;
|
|
|
+
|
|
|
+ mem += SATA_FSL_CMD_SLOT_SIZE;
|
|
|
+ mem_dma += SATA_FSL_CMD_SLOT_SIZE;
|
|
|
+
|
|
|
+ pp->cmdentry = mem;
|
|
|
+ pp->cmdentry_paddr = mem_dma;
|
|
|
+
|
|
|
+ ap->private_data = pp;
|
|
|
+
|
|
|
+ VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
|
|
|
+ pp->cmdslot_paddr, pp->cmdentry_paddr);
|
|
|
+
|
|
|
+ /* Now, update the CHBA register in host controller cmd register set */
|
|
|
+ iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Now, we can bring the controller on-line & also initiate
|
|
|
+ * the COMINIT sequence, we simply return here and the boot-probing
|
|
|
+ * & device discovery process is re-initiated by libATA using a
|
|
|
+ * Softreset EH (dummy) session. Hence, boot probing and device
|
|
|
+ * discovey will be part of sata_fsl_softreset() callback.
|
|
|
+ */
|
|
|
+
|
|
|
+ temp = ioread32(hcr_base + HCONTROL);
|
|
|
+ iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
|
|
|
+
|
|
|
+ VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
|
|
|
+ VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
|
|
|
+ VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Workaround for 8315DS board 3gbps link-up issue,
|
|
|
+ * currently limit SATA port to GEN1 speed
|
|
|
+ */
|
|
|
+ sata_fsl_scr_read(ap, SCR_CONTROL, &temp);
|
|
|
+ temp &= ~(0xF << 4);
|
|
|
+ temp |= (0x1 << 4);
|
|
|
+ sata_fsl_scr_write(ap, SCR_CONTROL, temp);
|
|
|
+
|
|
|
+ sata_fsl_scr_read(ap, SCR_CONTROL, &temp);
|
|
|
+ dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n",
|
|
|
+ temp);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void sata_fsl_port_stop(struct ata_port *ap)
|
|
|
+{
|
|
|
+ struct device *dev = ap->host->dev;
|
|
|
+ struct sata_fsl_port_priv *pp = ap->private_data;
|
|
|
+ struct sata_fsl_host_priv *host_priv = ap->host->private_data;
|
|
|
+ void __iomem *hcr_base = host_priv->hcr_base;
|
|
|
+ u32 temp;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Force host controller to go off-line, aborting current operations
|
|
|
+ */
|
|
|
+ temp = ioread32(hcr_base + HCONTROL);
|
|
|
+ temp &= ~HCONTROL_ONLINE_PHY_RST;
|
|
|
+ temp |= HCONTROL_FORCE_OFFLINE;
|
|
|
+ iowrite32(temp, hcr_base + HCONTROL);
|
|
|
+
|
|
|
+ /* Poll for controller to go offline - should happen immediately */
|
|
|
+ ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
|
|
|
+
|
|
|
+ ap->private_data = NULL;
|
|
|
+ dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
|
|
|
+ pp->cmdslot, pp->cmdslot_paddr);
|
|
|
+
|
|
|
+ ata_pad_free(ap, dev);
|
|
|
+ kfree(pp);
|
|
|
+}
|
|
|
+
|
|
|
+static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
|
|
|
+{
|
|
|
+ struct sata_fsl_host_priv *host_priv = ap->host->private_data;
|
|
|
+ void __iomem *hcr_base = host_priv->hcr_base;
|
|
|
+ struct ata_taskfile tf;
|
|
|
+ u32 temp;
|
|
|
+
|
|
|
+ temp = ioread32(hcr_base + SIGNATURE);
|
|
|
+
|
|
|
+ VPRINTK("raw sig = 0x%x\n", temp);
|
|
|
+ VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
|
|
|
+ VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
|
|
|
+
|
|
|
+ tf.lbah = (temp >> 24) & 0xff;
|
|
|
+ tf.lbam = (temp >> 16) & 0xff;
|
|
|
+ tf.lbal = (temp >> 8) & 0xff;
|
|
|
+ tf.nsect = temp & 0xff;
|
|
|
+
|
|
|
+ return ata_dev_classify(&tf);
|
|
|
+}
|
|
|
+
|
|
|
+static int sata_fsl_softreset(struct ata_port *ap, unsigned int *class,
|
|
|
+ unsigned long deadline)
|
|
|
+{
|
|
|
+ struct sata_fsl_port_priv *pp = ap->private_data;
|
|
|
+ struct sata_fsl_host_priv *host_priv = ap->host->private_data;
|
|
|
+ void __iomem *hcr_base = host_priv->hcr_base;
|
|
|
+ u32 temp;
|
|
|
+ struct ata_taskfile tf;
|
|
|
+ u8 *cfis;
|
|
|
+ u32 Serror;
|
|
|
+ int i = 0;
|
|
|
+ struct ata_queued_cmd qc;
|
|
|
+ u8 *buf;
|
|
|
+ dma_addr_t dma_address;
|
|
|
+ struct scatterlist *sg;
|
|
|
+ unsigned long start_jiffies;
|
|
|
+
|
|
|
+ DPRINTK("in xx_softreset\n");
|
|
|
+
|
|
|
+try_offline_again:
|
|
|
+ /*
|
|
|
+ * Force host controller to go off-line, aborting current operations
|
|
|
+ */
|
|
|
+ temp = ioread32(hcr_base + HCONTROL);
|
|
|
+ temp &= ~HCONTROL_ONLINE_PHY_RST;
|
|
|
+ iowrite32(temp, hcr_base + HCONTROL);
|
|
|
+
|
|
|
+ /* Poll for controller to go offline */
|
|
|
+ temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500);
|
|
|
+
|
|
|
+ if (temp & ONLINE) {
|
|
|
+ ata_port_printk(ap, KERN_ERR,
|
|
|
+ "Softreset failed, not off-lined %d\n", i);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Try to offline controller atleast twice
|
|
|
+ */
|
|
|
+ i++;
|
|
|
+ if (i == 2)
|
|
|
+ goto err;
|
|
|
+ else
|
|
|
+ goto try_offline_again;
|
|
|
+ }
|
|
|
+
|
|
|
+ DPRINTK("softreset, controller off-lined\n");
|
|
|
+ VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
|
|
|
+ VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
|
|
|
+
|
|
|
+ /*
|
|
|
+ * PHY reset should remain asserted for atleast 1ms
|
|
|
+ */
|
|
|
+ msleep(1);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Now, bring the host controller online again, this can take time
|
|
|
+ * as PHY reset and communication establishment, 1st D2H FIS and
|
|
|
+ * device signature update is done, on safe side assume 500ms
|
|
|
+ * NOTE : Host online status may be indicated immediately!!
|
|
|
+ */
|
|
|
+
|
|
|
+ temp = ioread32(hcr_base + HCONTROL);
|
|
|
+ temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
|
|
|
+ iowrite32(temp, hcr_base + HCONTROL);
|
|
|
+
|
|
|
+ temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500);
|
|
|
+
|
|
|
+ if (!(temp & ONLINE)) {
|
|
|
+ ata_port_printk(ap, KERN_ERR,
|
|
|
+ "Softreset failed, not on-lined\n");
|
|
|
+ goto err;
|
|
|
+ }
|
|
|
+
|
|
|
+ DPRINTK("softreset, controller off-lined & on-lined\n");
|
|
|
+ VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
|
|
|
+ VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
|
|
|
+
|
|
|
+ /*
|
|
|
+ * First, wait for the PHYRDY change to occur before waiting for
|
|
|
+ * the signature, and also verify if SStatus indicates device
|
|
|
+ * presence
|
|
|
+ */
|
|
|
+
|
|
|
+ temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500);
|
|
|
+ if ((!(temp & 0x10)) || ata_port_offline(ap)) {
|
|
|
+ ata_port_printk(ap, KERN_WARNING,
|
|
|
+ "No Device OR PHYRDY change,Hstatus = 0x%x\n",
|
|
|
+ ioread32(hcr_base + HSTATUS));
|
|
|
+ goto err;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Wait for the first D2H from device,i.e,signature update notification
|
|
|
+ */
|
|
|
+ start_jiffies = jiffies;
|
|
|
+ temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10,
|
|
|
+ 500, jiffies_to_msecs(deadline - start_jiffies));
|
|
|
+
|
|
|
+ if ((temp & 0xFF) != 0x18) {
|
|
|
+ ata_port_printk(ap, KERN_WARNING, "No Signature Update\n");
|
|
|
+ goto err;
|
|
|
+ } else {
|
|
|
+ ata_port_printk(ap, KERN_INFO,
|
|
|
+ "Signature Update detected @ %d msecs\n",
|
|
|
+ jiffies_to_msecs(jiffies - start_jiffies));
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Send a device reset (SRST) explicitly on command slot #0
|
|
|
+ * Check : will the command queue (reg) be cleared during offlining ??
|
|
|
+ * Also we will be online only if Phy commn. has been established
|
|
|
+ * and device presence has been detected, therefore if we have
|
|
|
+ * reached here, we can send a command to the target device
|
|
|
+ */
|
|
|
+
|
|
|
+ if (ap->sactive)
|
|
|
+ goto skip_srst_do_ncq_error_handling;
|
|
|
+
|
|
|
+ DPRINTK("Sending SRST/device reset\n");
|
|
|
+
|
|
|
+ ata_tf_init(ap->device, &tf);
|
|
|
+ cfis = (u8 *) & pp->cmdentry->cfis;
|
|
|
+
|
|
|
+ /* device reset/SRST is a control register update FIS, uses tag0 */
|
|
|
+ sata_fsl_setup_cmd_hdr_entry(pp, 0,
|
|
|
+ SRST_CMD | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
|
|
|
+
|
|
|
+ tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
|
|
|
+ ata_tf_to_fis(&tf, 0, 0, cfis);
|
|
|
+
|
|
|
+ DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
|
|
|
+ cfis[0], cfis[1], cfis[2], cfis[3]);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Queue SRST command to the controller/device, ensure that no
|
|
|
+ * other commands are active on the controller/device
|
|
|
+ */
|
|
|
+
|
|
|
+ DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
|
|
|
+ ioread32(CQ + hcr_base),
|
|
|
+ ioread32(CA + hcr_base), ioread32(CC + hcr_base));
|
|
|
+
|
|
|
+ iowrite32(0xFFFF, CC + hcr_base);
|
|
|
+ iowrite32(1, CQ + hcr_base);
|
|
|
+
|
|
|
+ temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000);
|
|
|
+ if (temp & 0x1) {
|
|
|
+ ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n");
|
|
|
+
|
|
|
+ DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
|
|
|
+ ioread32(CQ + hcr_base),
|
|
|
+ ioread32(CA + hcr_base), ioread32(CC + hcr_base));
|
|
|
+
|
|
|
+ sata_fsl_scr_read(ap, SCR_ERROR, &Serror);
|
|
|
+
|
|
|
+ DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
|
|
|
+ DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
|
|
|
+ DPRINTK("Serror = 0x%x\n", Serror);
|
|
|
+ goto err;
|
|
|
+ }
|
|
|
+
|
|
|
+ msleep(1);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * SATA device enters reset state after receving a Control register
|
|
|
+ * FIS with SRST bit asserted and it awaits another H2D Control reg.
|
|
|
+ * FIS with SRST bit cleared, then the device does internal diags &
|
|
|
+ * initialization, followed by indicating it's initialization status
|
|
|
+ * using ATA signature D2H register FIS to the host controller.
|
|
|
+ */
|
|
|
+
|
|
|
+ sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
|
|
|
+
|
|
|
+ tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
|
|
|
+ ata_tf_to_fis(&tf, 0, 0, cfis);
|
|
|
+
|
|
|
+ iowrite32(1, CQ + hcr_base);
|
|
|
+ msleep(150); /* ?? */
|
|
|
+
|
|
|
+ /*
|
|
|
+ * The above command would have signalled an interrupt on command
|
|
|
+ * complete, which needs special handling, by clearing the Nth
|
|
|
+ * command bit of the CCreg
|
|
|
+ */
|
|
|
+ iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
|
|
|
+ goto check_device_signature;
|
|
|
+
|
|
|
+skip_srst_do_ncq_error_handling:
|
|
|
+
|
|
|
+ VPRINTK("Sending read log ext(10h) command\n");
|
|
|
+
|
|
|
+ memset(&qc, 0, sizeof(struct ata_queued_cmd));
|
|
|
+ ata_tf_init(ap->device, &tf);
|
|
|
+
|
|
|
+ tf.command = ATA_CMD_READ_LOG_EXT;
|
|
|
+ tf.lbal = ATA_LOG_SATA_NCQ;
|
|
|
+ tf.nsect = 1;
|
|
|
+ tf.hob_nsect = 0;
|
|
|
+ tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_LBA48 | ATA_TFLAG_DEVICE;
|
|
|
+ tf.protocol = ATA_PROT_PIO;
|
|
|
+
|
|
|
+ qc.tag = ATA_TAG_INTERNAL;
|
|
|
+ qc.scsicmd = NULL;
|
|
|
+ qc.ap = ap;
|
|
|
+ qc.dev = ap->device;
|
|
|
+
|
|
|
+ qc.tf = tf;
|
|
|
+ qc.flags |= ATA_QCFLAG_RESULT_TF;
|
|
|
+ qc.dma_dir = DMA_FROM_DEVICE;
|
|
|
+
|
|
|
+ buf = ap->sector_buf;
|
|
|
+ ata_sg_init_one(&qc, buf, 1 * ATA_SECT_SIZE);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Need to DMA-map the memory buffer associated with the command
|
|
|
+ */
|
|
|
+
|
|
|
+ sg = qc.__sg;
|
|
|
+ dma_address = dma_map_single(ap->dev, qc.buf_virt,
|
|
|
+ sg->length, DMA_FROM_DEVICE);
|
|
|
+
|
|
|
+ sg_dma_address(sg) = dma_address;
|
|
|
+ sg_dma_len(sg) = sg->length;
|
|
|
+
|
|
|
+ VPRINTK("EH, addr = 0x%x, len = 0x%x\n", dma_address, sg->length);
|
|
|
+
|
|
|
+ sata_fsl_qc_prep(&qc);
|
|
|
+ sata_fsl_qc_issue(&qc);
|
|
|
+
|
|
|
+ temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000);
|
|
|
+ if (temp & 0x1) {
|
|
|
+ VPRINTK("READ_LOG_EXT_10H issue failed\n");
|
|
|
+
|
|
|
+ VPRINTK("READ_LOG@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
|
|
|
+ ioread32(CQ + hcr_base),
|
|
|
+ ioread32(CA + hcr_base), ioread32(CC + hcr_base));
|
|
|
+
|
|
|
+ sata_fsl_scr_read(ap, SCR_ERROR, &Serror);
|
|
|
+
|
|
|
+ VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
|
|
|
+ VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
|
|
|
+ VPRINTK("Serror = 0x%x\n", Serror);
|
|
|
+ goto err;
|
|
|
+ }
|
|
|
+
|
|
|
+ iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
|
|
|
+
|
|
|
+ check_device_signature:
|
|
|
+
|
|
|
+ DPRINTK("SATA FSL : Now checking device signature\n");
|
|
|
+
|
|
|
+ *class = ATA_DEV_NONE;
|
|
|
+
|
|
|
+ /* Verify if SStatus indicates device presence */
|
|
|
+ if (ata_port_online(ap)) {
|
|
|
+ /*
|
|
|
+ * if we are here, device presence has been detected,
|
|
|
+ * 1st D2H FIS would have been received, but sfis in
|
|
|
+ * command desc. is not updated, but signature register
|
|
|
+ * would have been updated
|
|
|
+ */
|
|
|
+
|
|
|
+ *class = sata_fsl_dev_classify(ap);
|
|
|
+
|
|
|
+ DPRINTK("class = %d\n", *class);
|
|
|
+ VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
|
|
|
+ VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+
|
|
|
+err:
|
|
|
+ return -EIO;
|
|
|
+}
|
|
|
+
|
|
|
+static int sata_fsl_hardreset(struct ata_port *ap, unsigned int *class,
|
|
|
+ unsigned long deadline)
|
|
|
+{
|
|
|
+ int retval;
|
|
|
+
|
|
|
+ retval = sata_std_hardreset(ap, class, deadline);
|
|
|
+
|
|
|
+ DPRINTK("SATA FSL : in xx_hardreset, retval = 0x%d\n", retval);
|
|
|
+
|
|
|
+ return retval;
|
|
|
+}
|
|
|
+
|
|
|
+static void sata_fsl_error_handler(struct ata_port *ap)
|
|
|
+{
|
|
|
+
|
|
|
+ DPRINTK("in xx_error_handler\n");
|
|
|
+
|
|
|
+ /* perform recovery */
|
|
|
+ ata_do_eh(ap, ata_std_prereset, sata_fsl_softreset, sata_fsl_hardreset,
|
|
|
+ ata_std_postreset);
|
|
|
+}
|
|
|
+
|
|
|
+static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
|
|
|
+{
|
|
|
+ if (qc->flags & ATA_QCFLAG_FAILED)
|
|
|
+ qc->err_mask |= AC_ERR_OTHER;
|
|
|
+
|
|
|
+ if (qc->err_mask) {
|
|
|
+ /* make DMA engine forget about the failed command */
|
|
|
+
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void sata_fsl_irq_clear(struct ata_port *ap)
|
|
|
+{
|
|
|
+ /* unused */
|
|
|
+}
|
|
|
+
|
|
|
+static void sata_fsl_error_intr(struct ata_port *ap)
|
|
|
+{
|
|
|
+ struct ata_eh_info *ehi = &ap->eh_info;
|
|
|
+ struct sata_fsl_host_priv *host_priv = ap->host->private_data;
|
|
|
+ void __iomem *hcr_base = host_priv->hcr_base;
|
|
|
+ u32 hstatus, dereg, cereg = 0, SError = 0;
|
|
|
+ unsigned int err_mask = 0, action = 0;
|
|
|
+ struct ata_queued_cmd *qc;
|
|
|
+ int freeze = 0;
|
|
|
+
|
|
|
+ hstatus = ioread32(hcr_base + HSTATUS);
|
|
|
+ cereg = ioread32(hcr_base + CE);
|
|
|
+
|
|
|
+ ata_ehi_clear_desc(ehi);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Handle & Clear SError
|
|
|
+ */
|
|
|
+
|
|
|
+ sata_fsl_scr_read(ap, SCR_ERROR, &SError);
|
|
|
+ if (unlikely(SError & 0xFFFF0000)) {
|
|
|
+ sata_fsl_scr_write(ap, SCR_ERROR, SError);
|
|
|
+ err_mask |= AC_ERR_ATA_BUS;
|
|
|
+ }
|
|
|
+
|
|
|
+ DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
|
|
|
+ hstatus, cereg, ioread32(hcr_base + DE), SError);
|
|
|
+
|
|
|
+ /* handle single device errors */
|
|
|
+ if (cereg) {
|
|
|
+ /*
|
|
|
+ * clear the command error, also clears queue to the device
|
|
|
+ * in error, and we can (re)issue commands to this device.
|
|
|
+ * When a device is in error all commands queued into the
|
|
|
+ * host controller and at the device are considered aborted
|
|
|
+ * and the queue for that device is stopped. Now, after
|
|
|
+ * clearing the device error, we can issue commands to the
|
|
|
+ * device to interrogate it to find the source of the error.
|
|
|
+ */
|
|
|
+ dereg = ioread32(hcr_base + DE);
|
|
|
+ iowrite32(dereg, hcr_base + DE);
|
|
|
+ iowrite32(cereg, hcr_base + CE);
|
|
|
+
|
|
|
+ DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
|
|
|
+ ioread32(hcr_base + CE), ioread32(hcr_base + DE));
|
|
|
+ /*
|
|
|
+ * We should consider this as non fatal error, and TF must
|
|
|
+ * be updated as done below.
|
|
|
+ */
|
|
|
+
|
|
|
+ err_mask |= AC_ERR_DEV;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* handle fatal errors */
|
|
|
+ if (hstatus & FATAL_ERROR_DECODE) {
|
|
|
+ err_mask |= AC_ERR_ATA_BUS;
|
|
|
+ action |= ATA_EH_SOFTRESET;
|
|
|
+ /* how will fatal error interrupts be completed ?? */
|
|
|
+ freeze = 1;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Handle PHYRDY change notification */
|
|
|
+ if (hstatus & INT_ON_PHYRDY_CHG) {
|
|
|
+ DPRINTK("SATA FSL: PHYRDY change indication\n");
|
|
|
+
|
|
|
+ /* Setup a soft-reset EH action */
|
|
|
+ ata_ehi_hotplugged(ehi);
|
|
|
+ freeze = 1;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* record error info */
|
|
|
+ qc = ata_qc_from_tag(ap, ap->active_tag);
|
|
|
+
|
|
|
+ if (qc) {
|
|
|
+ sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap);
|
|
|
+ qc->err_mask |= err_mask;
|
|
|
+ } else
|
|
|
+ ehi->err_mask |= err_mask;
|
|
|
+
|
|
|
+ ehi->action |= action;
|
|
|
+ ehi->serror |= SError;
|
|
|
+
|
|
|
+ /* freeze or abort */
|
|
|
+ if (freeze)
|
|
|
+ ata_port_freeze(ap);
|
|
|
+ else
|
|
|
+ ata_port_abort(ap);
|
|
|
+}
|
|
|
+
|
|
|
+static void sata_fsl_qc_complete(struct ata_queued_cmd *qc)
|
|
|
+{
|
|
|
+ if (qc->flags & ATA_QCFLAG_RESULT_TF) {
|
|
|
+ DPRINTK("xx_qc_complete called\n");
|
|
|
+ sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void sata_fsl_host_intr(struct ata_port *ap)
|
|
|
+{
|
|
|
+ struct sata_fsl_host_priv *host_priv = ap->host->private_data;
|
|
|
+ void __iomem *hcr_base = host_priv->hcr_base;
|
|
|
+ u32 hstatus, qc_active = 0;
|
|
|
+ struct ata_queued_cmd *qc;
|
|
|
+ u32 SError;
|
|
|
+
|
|
|
+ hstatus = ioread32(hcr_base + HSTATUS);
|
|
|
+
|
|
|
+ sata_fsl_scr_read(ap, SCR_ERROR, &SError);
|
|
|
+
|
|
|
+ if (unlikely(SError & 0xFFFF0000)) {
|
|
|
+ DPRINTK("serror @host_intr : 0x%x\n", SError);
|
|
|
+ sata_fsl_error_intr(ap);
|
|
|
+
|
|
|
+ }
|
|
|
+
|
|
|
+ if (unlikely(hstatus & INT_ON_ERROR)) {
|
|
|
+ DPRINTK("error interrupt!!\n");
|
|
|
+ sata_fsl_error_intr(ap);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (ap->sactive) { /* only true for NCQ commands */
|
|
|
+ int i;
|
|
|
+ /* Read command completed register */
|
|
|
+ qc_active = ioread32(hcr_base + CC);
|
|
|
+ /* clear CC bit, this will also complete the interrupt */
|
|
|
+ iowrite32(qc_active, hcr_base + CC);
|
|
|
+
|
|
|
+ DPRINTK("Status of all queues :\n");
|
|
|
+ DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
|
|
|
+ qc_active, ioread32(hcr_base + CA),
|
|
|
+ ioread32(hcr_base + CE));
|
|
|
+
|
|
|
+ for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
|
|
|
+ if (qc_active & (1 << i)) {
|
|
|
+ qc = ata_qc_from_tag(ap, i);
|
|
|
+ if (qc) {
|
|
|
+ sata_fsl_qc_complete(qc);
|
|
|
+ ata_qc_complete(qc);
|
|
|
+ }
|
|
|
+ DPRINTK
|
|
|
+ ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
|
|
|
+ i, ioread32(hcr_base + CC),
|
|
|
+ ioread32(hcr_base + CA));
|
|
|
+ }
|
|
|
+ }
|
|
|
+ return;
|
|
|
+
|
|
|
+ } else if (ap->qc_active) {
|
|
|
+ iowrite32(1, hcr_base + CC);
|
|
|
+ qc = ata_qc_from_tag(ap, ap->active_tag);
|
|
|
+
|
|
|
+ DPRINTK("completing non-ncq cmd, tag=%d,CC=0x%x\n",
|
|
|
+ ap->active_tag, ioread32(hcr_base + CC));
|
|
|
+
|
|
|
+ if (qc) {
|
|
|
+ sata_fsl_qc_complete(qc);
|
|
|
+ ata_qc_complete(qc);
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ /* Spurious Interrupt!! */
|
|
|
+ DPRINTK("spurious interrupt!!, CC = 0x%x\n",
|
|
|
+ ioread32(hcr_base + CC));
|
|
|
+ return;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
|
|
|
+{
|
|
|
+ struct ata_host *host = dev_instance;
|
|
|
+ struct sata_fsl_host_priv *host_priv = host->private_data;
|
|
|
+ void __iomem *hcr_base = host_priv->hcr_base;
|
|
|
+ u32 interrupt_enables;
|
|
|
+ unsigned handled = 0;
|
|
|
+ struct ata_port *ap;
|
|
|
+
|
|
|
+ /* ack. any pending IRQs for this controller/port */
|
|
|
+ interrupt_enables = ioread32(hcr_base + HSTATUS);
|
|
|
+ interrupt_enables &= 0x3F;
|
|
|
+
|
|
|
+ DPRINTK("interrupt status 0x%x\n", interrupt_enables);
|
|
|
+
|
|
|
+ if (!interrupt_enables)
|
|
|
+ return IRQ_NONE;
|
|
|
+
|
|
|
+ spin_lock(&host->lock);
|
|
|
+
|
|
|
+ /* Assuming one port per host controller */
|
|
|
+
|
|
|
+ ap = host->ports[0];
|
|
|
+ if (ap) {
|
|
|
+ sata_fsl_host_intr(ap);
|
|
|
+ } else {
|
|
|
+ dev_printk(KERN_WARNING, host->dev,
|
|
|
+ "interrupt on disabled port 0\n");
|
|
|
+ }
|
|
|
+
|
|
|
+ iowrite32(interrupt_enables, hcr_base + HSTATUS);
|
|
|
+ handled = 1;
|
|
|
+
|
|
|
+ spin_unlock(&host->lock);
|
|
|
+
|
|
|
+ return IRQ_RETVAL(handled);
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * Multiple ports are represented by multiple SATA controllers with
|
|
|
+ * one port per controller
|
|
|
+ */
|
|
|
+static int sata_fsl_init_controller(struct ata_host *host)
|
|
|
+{
|
|
|
+ struct sata_fsl_host_priv *host_priv = host->private_data;
|
|
|
+ void __iomem *hcr_base = host_priv->hcr_base;
|
|
|
+ u32 temp;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * NOTE : We cannot bring the controller online before setting
|
|
|
+ * the CHBA, hence main controller initialization is done as
|
|
|
+ * part of the port_start() callback
|
|
|
+ */
|
|
|
+
|
|
|
+ /* ack. any pending IRQs for this controller/port */
|
|
|
+ temp = ioread32(hcr_base + HSTATUS);
|
|
|
+ if (temp & 0x3F)
|
|
|
+ iowrite32((temp & 0x3F), hcr_base + HSTATUS);
|
|
|
+
|
|
|
+ /* Keep interrupts disabled on the controller */
|
|
|
+ temp = ioread32(hcr_base + HCONTROL);
|
|
|
+ iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
|
|
|
+
|
|
|
+ /* Disable interrupt coalescing control(icc), for the moment */
|
|
|
+ DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
|
|
|
+ iowrite32(0x01000000, hcr_base + ICC);
|
|
|
+
|
|
|
+ /* clear error registers, SError is cleared by libATA */
|
|
|
+ iowrite32(0x00000FFFF, hcr_base + CE);
|
|
|
+ iowrite32(0x00000FFFF, hcr_base + DE);
|
|
|
+
|
|
|
+ /* initially assuming no Port multiplier, set CQPMP to 0 */
|
|
|
+ iowrite32(0x0, hcr_base + CQPMP);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * host controller will be brought on-line, during xx_port_start()
|
|
|
+ * callback, that should also initiate the OOB, COMINIT sequence
|
|
|
+ */
|
|
|
+
|
|
|
+ DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
|
|
|
+ DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * scsi mid-layer and libata interface structures
|
|
|
+ */
|
|
|
+static struct scsi_host_template sata_fsl_sht = {
|
|
|
+ .module = THIS_MODULE,
|
|
|
+ .name = "sata_fsl",
|
|
|
+ .ioctl = ata_scsi_ioctl,
|
|
|
+ .queuecommand = ata_scsi_queuecmd,
|
|
|
+ .change_queue_depth = ata_scsi_change_queue_depth,
|
|
|
+ .can_queue = SATA_FSL_QUEUE_DEPTH,
|
|
|
+ .this_id = ATA_SHT_THIS_ID,
|
|
|
+ .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
|
|
|
+ .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
|
|
|
+ .emulated = ATA_SHT_EMULATED,
|
|
|
+ .use_clustering = ATA_SHT_USE_CLUSTERING,
|
|
|
+ .proc_name = "sata_fsl",
|
|
|
+ .dma_boundary = ATA_DMA_BOUNDARY,
|
|
|
+ .slave_configure = ata_scsi_slave_config,
|
|
|
+ .slave_destroy = ata_scsi_slave_destroy,
|
|
|
+ .bios_param = ata_std_bios_param,
|
|
|
+#ifdef CONFIG_PM
|
|
|
+ .suspend = ata_scsi_device_suspend,
|
|
|
+ .resume = ata_scsi_device_resume,
|
|
|
+#endif
|
|
|
+};
|
|
|
+
|
|
|
+static const struct ata_port_operations sata_fsl_ops = {
|
|
|
+ .port_disable = ata_port_disable,
|
|
|
+
|
|
|
+ .check_status = sata_fsl_check_status,
|
|
|
+ .check_altstatus = sata_fsl_check_status,
|
|
|
+ .dev_select = ata_noop_dev_select,
|
|
|
+
|
|
|
+ .tf_read = sata_fsl_tf_read,
|
|
|
+
|
|
|
+ .qc_prep = sata_fsl_qc_prep,
|
|
|
+ .qc_issue = sata_fsl_qc_issue,
|
|
|
+ .irq_clear = sata_fsl_irq_clear,
|
|
|
+ .irq_on = ata_dummy_irq_on,
|
|
|
+ .irq_ack = ata_dummy_irq_ack,
|
|
|
+
|
|
|
+ .scr_read = sata_fsl_scr_read,
|
|
|
+ .scr_write = sata_fsl_scr_write,
|
|
|
+
|
|
|
+ .freeze = sata_fsl_freeze,
|
|
|
+ .thaw = sata_fsl_thaw,
|
|
|
+ .error_handler = sata_fsl_error_handler,
|
|
|
+ .post_internal_cmd = sata_fsl_post_internal_cmd,
|
|
|
+
|
|
|
+ .port_start = sata_fsl_port_start,
|
|
|
+ .port_stop = sata_fsl_port_stop,
|
|
|
+};
|
|
|
+
|
|
|
+static const struct ata_port_info sata_fsl_port_info[] = {
|
|
|
+ {
|
|
|
+ .flags = SATA_FSL_HOST_FLAGS,
|
|
|
+ .pio_mask = 0x1f, /* pio 0-4 */
|
|
|
+ .udma_mask = 0x7f, /* udma 0-6 */
|
|
|
+ .port_ops = &sata_fsl_ops,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static int sata_fsl_probe(struct of_device *ofdev,
|
|
|
+ const struct of_device_id *match)
|
|
|
+{
|
|
|
+ int retval = 0;
|
|
|
+ void __iomem *hcr_base = NULL;
|
|
|
+ void __iomem *ssr_base = NULL;
|
|
|
+ void __iomem *csr_base = NULL;
|
|
|
+ struct sata_fsl_host_priv *host_priv = NULL;
|
|
|
+ struct resource *r;
|
|
|
+ int irq;
|
|
|
+ struct ata_host *host;
|
|
|
+
|
|
|
+ struct ata_port_info pi = sata_fsl_port_info[0];
|
|
|
+ const struct ata_port_info *ppi[] = { &pi, NULL };
|
|
|
+
|
|
|
+ dev_printk(KERN_INFO, &ofdev->dev,
|
|
|
+ "Sata FSL Platform/CSB Driver init\n");
|
|
|
+
|
|
|
+ r = kmalloc(sizeof(struct resource), GFP_KERNEL);
|
|
|
+
|
|
|
+ hcr_base = of_iomap(ofdev->node, 0);
|
|
|
+ if (!hcr_base)
|
|
|
+ goto error_exit_with_cleanup;
|
|
|
+
|
|
|
+ ssr_base = hcr_base + 0x100;
|
|
|
+ csr_base = hcr_base + 0x140;
|
|
|
+
|
|
|
+ DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
|
|
|
+ DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
|
|
|
+ DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
|
|
|
+
|
|
|
+ host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
|
|
|
+ if (!host_priv)
|
|
|
+ goto error_exit_with_cleanup;
|
|
|
+
|
|
|
+ host_priv->hcr_base = hcr_base;
|
|
|
+ host_priv->ssr_base = ssr_base;
|
|
|
+ host_priv->csr_base = csr_base;
|
|
|
+
|
|
|
+ irq = irq_of_parse_and_map(ofdev->node, 0);
|
|
|
+ if (irq < 0) {
|
|
|
+ dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n");
|
|
|
+ goto error_exit_with_cleanup;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* allocate host structure */
|
|
|
+ host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
|
|
|
+
|
|
|
+ /* host->iomap is not used currently */
|
|
|
+ host->private_data = host_priv;
|
|
|
+
|
|
|
+ /* setup port(s) */
|
|
|
+
|
|
|
+ host->ports[0]->ioaddr.cmd_addr = host_priv->hcr_base;
|
|
|
+ host->ports[0]->ioaddr.scr_addr = host_priv->ssr_base;
|
|
|
+
|
|
|
+ /* initialize host controller */
|
|
|
+ sata_fsl_init_controller(host);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Now, register with libATA core, this will also initiate the
|
|
|
+ * device discovery process, invoking our port_start() handler &
|
|
|
+ * error_handler() to execute a dummy Softreset EH session
|
|
|
+ */
|
|
|
+ ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
|
|
|
+ &sata_fsl_sht);
|
|
|
+
|
|
|
+ dev_set_drvdata(&ofdev->dev, host);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+
|
|
|
+error_exit_with_cleanup:
|
|
|
+
|
|
|
+ if (hcr_base)
|
|
|
+ iounmap(hcr_base);
|
|
|
+ if (host_priv)
|
|
|
+ kfree(host_priv);
|
|
|
+
|
|
|
+ return retval;
|
|
|
+}
|
|
|
+
|
|
|
+static int sata_fsl_remove(struct of_device *ofdev)
|
|
|
+{
|
|
|
+ struct ata_host *host = dev_get_drvdata(&ofdev->dev);
|
|
|
+ struct sata_fsl_host_priv *host_priv = host->private_data;
|
|
|
+
|
|
|
+ ata_host_detach(host);
|
|
|
+
|
|
|
+ dev_set_drvdata(&ofdev->dev, NULL);
|
|
|
+
|
|
|
+ irq_dispose_mapping(host->irq);
|
|
|
+ iounmap(host_priv->hcr_base);
|
|
|
+ kfree(host_priv);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static struct of_device_id fsl_sata_match[] = {
|
|
|
+ {
|
|
|
+ .compatible = "fsl,mpc8315-sata",
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .compatible = "fsl,mpc8379-sata",
|
|
|
+ },
|
|
|
+ {},
|
|
|
+};
|
|
|
+
|
|
|
+MODULE_DEVICE_TABLE(of, fsl_sata_match);
|
|
|
+
|
|
|
+static struct of_platform_driver fsl_sata_driver = {
|
|
|
+ .name = "fsl-sata",
|
|
|
+ .match_table = fsl_sata_match,
|
|
|
+ .probe = sata_fsl_probe,
|
|
|
+ .remove = sata_fsl_remove,
|
|
|
+};
|
|
|
+
|
|
|
+static int __init sata_fsl_init(void)
|
|
|
+{
|
|
|
+ of_register_platform_driver(&fsl_sata_driver);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void __exit sata_fsl_exit(void)
|
|
|
+{
|
|
|
+ of_unregister_platform_driver(&fsl_sata_driver);
|
|
|
+}
|
|
|
+
|
|
|
+MODULE_LICENSE("GPL");
|
|
|
+MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
|
|
|
+MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
|
|
|
+MODULE_VERSION("1.10");
|
|
|
+
|
|
|
+module_init(sata_fsl_init);
|
|
|
+module_exit(sata_fsl_exit);
|
Linus Torvalds