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@@ -447,34 +447,6 @@ out:
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return ret;
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}
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-static void __cpuinit probe_tlb(unsigned long config)
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-{
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- struct cpuinfo_mips *c = ¤t_cpu_data;
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- unsigned int reg;
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-
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- /*
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- * If this isn't a MIPS32 / MIPS64 compliant CPU. Config 1 register
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- * is not supported, we assume R4k style. Cpu probing already figured
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- * out the number of tlb entries.
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- */
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- if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY)
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- return;
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-#ifdef CONFIG_MIPS_MT_SMTC
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- /*
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- * If TLB is shared in SMTC system, total size already
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- * has been calculated and written into cpu_data tlbsize
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- */
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- if((smtc_status & SMTC_TLB_SHARED) == SMTC_TLB_SHARED)
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- return;
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-#endif /* CONFIG_MIPS_MT_SMTC */
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-
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- reg = read_c0_config1();
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- if (!((config >> 7) & 3))
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- panic("No TLB present");
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-
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- c->tlbsize = ((reg >> 25) & 0x3f) + 1;
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-}
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-
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static int __cpuinitdata ntlb;
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static int __init set_ntlb(char *str)
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{
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@@ -486,8 +458,6 @@ __setup("ntlb=", set_ntlb);
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void __cpuinit tlb_init(void)
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{
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- unsigned int config = read_c0_config();
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-
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/*
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* You should never change this register:
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* - On R4600 1.7 the tlbp never hits for pages smaller than
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@@ -495,7 +465,6 @@ void __cpuinit tlb_init(void)
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* - The entire mm handling assumes the c0_pagemask register to
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* be set to fixed-size pages.
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*/
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- probe_tlb(config);
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write_c0_pagemask(PM_DEFAULT_MASK);
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write_c0_wired(0);
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if (current_cpu_type() == CPU_R10000 ||
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