|
@@ -44,12 +44,12 @@
|
|
|
#define MII_VSC8244_ISTAT_DUPLEX 0x1000
|
|
|
|
|
|
/* Vitesse Auxiliary Control/Status Register */
|
|
|
-#define MII_VSC8244_AUX_CONSTAT 0x1c
|
|
|
-#define MII_VSC8244_AUXCONSTAT_INIT 0x0000
|
|
|
-#define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
|
|
|
-#define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
|
|
|
-#define MII_VSC8244_AUXCONSTAT_GBIT 0x0010
|
|
|
-#define MII_VSC8244_AUXCONSTAT_100 0x0008
|
|
|
+#define MII_VSC8244_AUX_CONSTAT 0x1c
|
|
|
+#define MII_VSC8244_AUXCONSTAT_INIT 0x0000
|
|
|
+#define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
|
|
|
+#define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
|
|
|
+#define MII_VSC8244_AUXCONSTAT_GBIT 0x0010
|
|
|
+#define MII_VSC8244_AUXCONSTAT_100 0x0008
|
|
|
|
|
|
#define MII_VSC8221_AUXCONSTAT_INIT 0x0004 /* need to set this bit? */
|
|
|
#define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004
|
|
@@ -100,9 +100,8 @@ static int vsc824x_config_init(struct phy_device *phydev)
|
|
|
static int vsc824x_ack_interrupt(struct phy_device *phydev)
|
|
|
{
|
|
|
int err = 0;
|
|
|
-
|
|
|
- /*
|
|
|
- * Don't bother to ACK the interrupts if interrupts
|
|
|
+
|
|
|
+ /* Don't bother to ACK the interrupts if interrupts
|
|
|
* are disabled. The 824x cannot clear the interrupts
|
|
|
* if they are disabled.
|
|
|
*/
|
|
@@ -122,8 +121,7 @@ static int vsc82xx_config_intr(struct phy_device *phydev)
|
|
|
MII_VSC8244_IMASK_MASK :
|
|
|
MII_VSC8221_IMASK_MASK);
|
|
|
else {
|
|
|
- /*
|
|
|
- * The Vitesse PHY cannot clear the interrupt
|
|
|
+ /* The Vitesse PHY cannot clear the interrupt
|
|
|
* once it has disabled them, so we clear them first
|
|
|
*/
|
|
|
err = phy_read(phydev, MII_VSC8244_ISTAT);
|
|
@@ -146,7 +144,8 @@ static int vsc8221_config_init(struct phy_device *phydev)
|
|
|
return err;
|
|
|
|
|
|
/* Perhaps we should set EXT_CON1 based on the interface?
|
|
|
- Options are 802.3Z SerDes or SGMII */
|
|
|
+ * Options are 802.3Z SerDes or SGMII
|
|
|
+ */
|
|
|
}
|
|
|
|
|
|
/* Vitesse 824x */
|