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@@ -93,7 +93,7 @@ ENTRY(cpu_feroceon_reset)
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*
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*
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* Called with IRQs disabled
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* Called with IRQs disabled
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*/
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*/
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- .align 10
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+ .align 5
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ENTRY(cpu_feroceon_do_idle)
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ENTRY(cpu_feroceon_do_idle)
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mov r0, #0
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
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mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
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@@ -106,6 +106,7 @@ ENTRY(cpu_feroceon_do_idle)
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* Clean and invalidate all cache entries in a particular
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* Clean and invalidate all cache entries in a particular
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* address space.
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* address space.
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*/
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*/
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+ .align 5
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ENTRY(feroceon_flush_user_cache_all)
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ENTRY(feroceon_flush_user_cache_all)
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/* FALLTHROUGH */
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/* FALLTHROUGH */
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@@ -118,12 +119,8 @@ ENTRY(feroceon_flush_kern_cache_all)
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mov r2, #VM_EXEC
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mov r2, #VM_EXEC
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mov ip, #0
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mov ip, #0
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__flush_whole_cache:
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__flush_whole_cache:
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-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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- mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
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-#else
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1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
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1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
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bne 1b
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bne 1b
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-#endif
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tst r2, #VM_EXEC
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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@@ -139,27 +136,19 @@ __flush_whole_cache:
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* - end - end address (exclusive)
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* - end - end address (exclusive)
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* - flags - vm_flags describing address space
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* - flags - vm_flags describing address space
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*/
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*/
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+ .align 5
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ENTRY(feroceon_flush_user_cache_range)
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ENTRY(feroceon_flush_user_cache_range)
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mov ip, #0
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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sub r3, r1, r0 @ calculate total size
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cmp r3, #CACHE_DLIMIT
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cmp r3, #CACHE_DLIMIT
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bgt __flush_whole_cache
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bgt __flush_whole_cache
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1: tst r2, #VM_EXEC
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1: tst r2, #VM_EXEC
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-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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- mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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- mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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- add r0, r0, #CACHE_DLINESIZE
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- mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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- mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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- add r0, r0, #CACHE_DLINESIZE
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-#else
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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add r0, r0, #CACHE_DLINESIZE
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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add r0, r0, #CACHE_DLINESIZE
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-#endif
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cmp r0, r1
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cmp r0, r1
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blo 1b
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blo 1b
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tst r2, #VM_EXEC
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tst r2, #VM_EXEC
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@@ -176,6 +165,7 @@ ENTRY(feroceon_flush_user_cache_range)
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* - start - virtual start address
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* - start - virtual start address
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* - end - virtual end address
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* - end - virtual end address
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*/
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*/
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+ .align 5
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ENTRY(feroceon_coherent_kern_range)
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ENTRY(feroceon_coherent_kern_range)
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/* FALLTHROUGH */
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/* FALLTHROUGH */
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@@ -207,6 +197,7 @@ ENTRY(feroceon_coherent_user_range)
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*
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*
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* - addr - page aligned address
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* - addr - page aligned address
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*/
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*/
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+ .align 5
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ENTRY(feroceon_flush_kern_dcache_page)
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ENTRY(feroceon_flush_kern_dcache_page)
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add r1, r0, #PAGE_SZ
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add r1, r0, #PAGE_SZ
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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@@ -231,13 +222,12 @@ ENTRY(feroceon_flush_kern_dcache_page)
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*
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*
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* (same as v4wb)
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* (same as v4wb)
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*/
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*/
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+ .align 5
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ENTRY(feroceon_dma_inv_range)
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ENTRY(feroceon_dma_inv_range)
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-#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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tst r0, #CACHE_DLINESIZE - 1
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tst r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHE_DLINESIZE - 1
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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-#endif
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bic r0, r0, #CACHE_DLINESIZE - 1
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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add r0, r0, #CACHE_DLINESIZE
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@@ -256,14 +246,13 @@ ENTRY(feroceon_dma_inv_range)
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*
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*
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* (same as v4wb)
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* (same as v4wb)
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*/
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*/
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+ .align 5
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ENTRY(feroceon_dma_clean_range)
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ENTRY(feroceon_dma_clean_range)
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-#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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bic r0, r0, #CACHE_DLINESIZE - 1
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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cmp r0, r1
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blo 1b
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blo 1b
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-#endif
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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mov pc, lr
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@@ -275,14 +264,10 @@ ENTRY(feroceon_dma_clean_range)
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* - start - virtual start address
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* - start - virtual start address
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* - end - virtual end address
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* - end - virtual end address
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*/
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*/
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+ .align 5
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ENTRY(feroceon_dma_flush_range)
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ENTRY(feroceon_dma_flush_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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bic r0, r0, #CACHE_DLINESIZE - 1
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-1:
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-#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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- mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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-#else
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- mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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-#endif
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+1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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cmp r0, r1
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blo 1b
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blo 1b
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@@ -300,13 +285,12 @@ ENTRY(feroceon_cache_fns)
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.long feroceon_dma_clean_range
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.long feroceon_dma_clean_range
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.long feroceon_dma_flush_range
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.long feroceon_dma_flush_range
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+ .align 5
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ENTRY(cpu_feroceon_dcache_clean_area)
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ENTRY(cpu_feroceon_dcache_clean_area)
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-#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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add r0, r0, #CACHE_DLINESIZE
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subs r1, r1, #CACHE_DLINESIZE
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subs r1, r1, #CACHE_DLINESIZE
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bhi 1b
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bhi 1b
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-#endif
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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mov pc, lr
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@@ -323,13 +307,9 @@ ENTRY(cpu_feroceon_dcache_clean_area)
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ENTRY(cpu_feroceon_switch_mm)
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ENTRY(cpu_feroceon_switch_mm)
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#ifdef CONFIG_MMU
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#ifdef CONFIG_MMU
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mov ip, #0
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mov ip, #0
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-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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- mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
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-#else
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@ && 'Clean & Invalidate whole DCache'
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@ && 'Clean & Invalidate whole DCache'
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1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
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1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
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bne 1b
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bne 1b
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-#endif
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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@@ -362,16 +342,9 @@ ENTRY(cpu_feroceon_set_pte_ext)
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tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
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tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
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movne r2, #0
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movne r2, #0
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-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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- eor r3, r2, #0x0a @ C & small page?
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- tst r3, #0x0b
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- biceq r2, r2, #4
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-#endif
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str r2, [r0] @ hardware version
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str r2, [r0] @ hardware version
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mov r0, r0
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mov r0, r0
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-#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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-#endif
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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#endif
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#endif
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mov pc, lr
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mov pc, lr
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@@ -387,20 +360,11 @@ __feroceon_setup:
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mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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#endif
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#endif
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-
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-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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- mov r0, #4 @ disable write-back on caches explicitly
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- mcr p15, 7, r0, c15, c0, 0
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-#endif
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-
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adr r5, feroceon_crval
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adr r5, feroceon_crval
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ldmia r5, {r5, r6}
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ldmia r5, {r5, r6}
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mrc p15, 0, r0, c1, c0 @ get control register v4
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mrc p15, 0, r0, c1, c0 @ get control register v4
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bic r0, r0, r5
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bic r0, r0, r5
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orr r0, r0, r6
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orr r0, r0, r6
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-#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
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- orr r0, r0, #0x4000 @ .1.. .... .... ....
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-#endif
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mov pc, lr
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mov pc, lr
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.size __feroceon_setup, . - __feroceon_setup
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.size __feroceon_setup, . - __feroceon_setup
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@@ -476,7 +440,7 @@ __feroceon_old_id_proc_info:
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.long cpu_feroceon_name
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.long cpu_feroceon_name
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.long feroceon_processor_functions
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.long feroceon_processor_functions
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.long v4wbi_tlb_fns
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.long v4wbi_tlb_fns
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- .long v4wb_user_fns
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+ .long feroceon_user_fns
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.long feroceon_cache_fns
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.long feroceon_cache_fns
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.size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
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.size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
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#endif
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#endif
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@@ -502,6 +466,6 @@ __feroceon_proc_info:
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.long cpu_feroceon_name
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.long cpu_feroceon_name
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.long feroceon_processor_functions
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.long feroceon_processor_functions
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.long v4wbi_tlb_fns
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.long v4wbi_tlb_fns
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- .long v4wb_user_fns
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+ .long feroceon_user_fns
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.long feroceon_cache_fns
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.long feroceon_cache_fns
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.size __feroceon_proc_info, . - __feroceon_proc_info
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.size __feroceon_proc_info, . - __feroceon_proc_info
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