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@@ -36,6 +36,9 @@
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#define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
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#define ESDHC_WTMK_LVL 0x44
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#define ESDHC_MIX_CTRL 0x48
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+#define ESDHC_MIX_CTRL_AC23EN (1 << 7)
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+/* Bits 3 and 6 are not SDHCI standard definitions */
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+#define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
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/*
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* There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
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@@ -251,7 +254,12 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
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if (is_imx6q_usdhc(imx_data)) {
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u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
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- m = val | (m & 0xffff0000);
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+ /* Swap AC23 bit */
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+ if (val & SDHCI_TRNS_AUTO_CMD23) {
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+ val &= ~SDHCI_TRNS_AUTO_CMD23;
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+ val |= ESDHC_MIX_CTRL_AC23EN;
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+ }
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+ m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
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writel(m, host->ioaddr + ESDHC_MIX_CTRL);
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} else {
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/*
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