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@@ -151,46 +151,54 @@ void tm6000_set_fourcc_format(struct tm6000_core *dev)
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int tm6000_init_analog_mode (struct tm6000_core *dev)
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int tm6000_init_analog_mode (struct tm6000_core *dev)
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{
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{
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+ if (dev->dev_type == TM6010) {
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+ int val;
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- /* Enables soft reset */
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- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x3f, 0x01);
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+ /* Enable video */
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+ val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, 0);
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+ val |= 0x60;
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+ tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, val);
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+ tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xfe, 0xcf);
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- if (dev->scaler) {
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- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc0, 0x20);
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} else {
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} else {
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- /* Enable Hfilter and disable TS Drop err */
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- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc0, 0x80);
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- }
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- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc3, 0x88);
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- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xda, 0x23);
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- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xd1, 0xc0);
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- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xd2, 0xd8);
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- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xd6, 0x06);
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- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xdf, 0x1f);
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-
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- /* AP Software reset */
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- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xff, 0x08);
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- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xff, 0x00);
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+ /* Enables soft reset */
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+ tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x3f, 0x01);
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+
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+ if (dev->scaler) {
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+ tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0x20);
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+ } else {
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+ /* Enable Hfilter and disable TS Drop err */
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+ tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0x80);
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+ }
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- tm6000_set_fourcc_format(dev);
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+ tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc3, 0x88);
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+ tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xda, 0x23);
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+ tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd1, 0xc0);
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+ tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd2, 0xd8);
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+ tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd6, 0x06);
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+ tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xdf, 0x1f);
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- /* Disables soft reset */
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- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x3f, 0x00);
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+ /* AP Software reset */
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+ tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xff, 0x08);
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+ tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xff, 0x00);
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- /* E3: Select input 0 - TV tuner */
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- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xe3, 0x00);
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- tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60);
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+ tm6000_set_fourcc_format(dev);
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- /* Tuner firmware can now be loaded */
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+ /* Disables soft reset */
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+ tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x3f, 0x00);
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- tm6000_set_reg (dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_1, 0x00);
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- msleep(11);
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+ /* E3: Select input 0 - TV tuner */
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+ tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xe3, 0x00);
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+ tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60);
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- /* This controls input */
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- tm6000_set_reg (dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_2, 0x0);
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- tm6000_set_reg (dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_3, 0x01);
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+ /* This controls input */
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+ tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_2, 0x0);
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+ tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_3, 0x01);
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+ }
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msleep(20);
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msleep(20);
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+ /* Tuner firmware can now be loaded */
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+
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/*FIXME: Hack!!! */
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/*FIXME: Hack!!! */
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struct v4l2_frequency f;
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struct v4l2_frequency f;
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mutex_lock(&dev->lock);
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mutex_lock(&dev->lock);
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@@ -202,7 +210,6 @@ int tm6000_init_analog_mode (struct tm6000_core *dev)
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tm6000_set_standard (dev, &dev->norm);
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tm6000_set_standard (dev, &dev->norm);
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tm6000_set_audio_bitrate (dev,48000);
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tm6000_set_audio_bitrate (dev,48000);
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-
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return 0;
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return 0;
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}
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}
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@@ -238,88 +245,183 @@ int tm6000_init_digital_mode (struct tm6000_core *dev)
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return 0;
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return 0;
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}
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}
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+struct reg_init {
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+ u8 req;
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+ u8 reg;
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+ u8 val;
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+};
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+
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/* The meaning of those initializations are unknown */
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/* The meaning of those initializations are unknown */
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-u8 init_tab[][2] = {
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+struct reg_init tm6000_init_tab[] = {
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/* REG VALUE */
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/* REG VALUE */
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- { 0xdf, 0x1f },
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- { 0xff, 0x08 },
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- { 0xff, 0x00 },
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- { 0xd5, 0x4f },
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- { 0xda, 0x23 },
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- { 0xdb, 0x08 },
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- { 0xe2, 0x00 },
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- { 0xe3, 0x10 },
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- { 0xe5, 0x00 },
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- { 0xe8, 0x00 },
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- { 0xeb, 0x64 }, /* 48000 bits/sample, external input */
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- { 0xee, 0xc2 },
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- { 0x3f, 0x01 }, /* Start of soft reset */
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- { 0x00, 0x00 },
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- { 0x01, 0x07 },
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- { 0x02, 0x5f },
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- { 0x03, 0x00 },
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- { 0x05, 0x64 },
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- { 0x07, 0x01 },
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- { 0x08, 0x82 },
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- { 0x09, 0x36 },
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- { 0x0a, 0x50 },
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- { 0x0c, 0x6a },
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- { 0x11, 0xc9 },
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- { 0x12, 0x07 },
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- { 0x13, 0x3b },
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- { 0x14, 0x47 },
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- { 0x15, 0x6f },
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- { 0x17, 0xcd },
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- { 0x18, 0x1e },
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- { 0x19, 0x8b },
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- { 0x1a, 0xa2 },
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- { 0x1b, 0xe9 },
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- { 0x1c, 0x1c },
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- { 0x1d, 0xcc },
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- { 0x1e, 0xcc },
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- { 0x1f, 0xcd },
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- { 0x20, 0x3c },
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- { 0x21, 0x3c },
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- { 0x2d, 0x48 },
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- { 0x2e, 0x88 },
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- { 0x30, 0x22 },
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- { 0x31, 0x61 },
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- { 0x32, 0x74 },
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- { 0x33, 0x1c },
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- { 0x34, 0x74 },
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- { 0x35, 0x1c },
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- { 0x36, 0x7a },
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- { 0x37, 0x26 },
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- { 0x38, 0x40 },
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- { 0x39, 0x0a },
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- { 0x42, 0x55 },
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- { 0x51, 0x11 },
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- { 0x55, 0x01 },
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- { 0x57, 0x02 },
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- { 0x58, 0x35 },
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- { 0x59, 0xa0 },
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- { 0x80, 0x15 },
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- { 0x82, 0x42 },
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- { 0xc1, 0xd0 },
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- { 0xc3, 0x88 },
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- { 0x3f, 0x00 }, /* End of the soft reset */
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+ { REQ_07_SET_GET_AVREG, 0xdf, 0x1f },
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+ { REQ_07_SET_GET_AVREG, 0xff, 0x08 },
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+ { REQ_07_SET_GET_AVREG, 0xff, 0x00 },
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+ { REQ_07_SET_GET_AVREG, 0xd5, 0x4f },
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+ { REQ_07_SET_GET_AVREG, 0xda, 0x23 },
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+ { REQ_07_SET_GET_AVREG, 0xdb, 0x08 },
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+ { REQ_07_SET_GET_AVREG, 0xe2, 0x00 },
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+ { REQ_07_SET_GET_AVREG, 0xe3, 0x10 },
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+ { REQ_07_SET_GET_AVREG, 0xe5, 0x00 },
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+ { REQ_07_SET_GET_AVREG, 0xe8, 0x00 },
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+ { REQ_07_SET_GET_AVREG, 0xeb, 0x64 }, /* 48000 bits/sample, external input */
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+ { REQ_07_SET_GET_AVREG, 0xee, 0xc2 },
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+ { REQ_07_SET_GET_AVREG, 0x3f, 0x01 }, /* Start of soft reset */
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+ { REQ_07_SET_GET_AVREG, 0x00, 0x00 },
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+ { REQ_07_SET_GET_AVREG, 0x01, 0x07 },
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+ { REQ_07_SET_GET_AVREG, 0x02, 0x5f },
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+ { REQ_07_SET_GET_AVREG, 0x03, 0x00 },
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+ { REQ_07_SET_GET_AVREG, 0x05, 0x64 },
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+ { REQ_07_SET_GET_AVREG, 0x07, 0x01 },
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+ { REQ_07_SET_GET_AVREG, 0x08, 0x82 },
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+ { REQ_07_SET_GET_AVREG, 0x09, 0x36 },
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+ { REQ_07_SET_GET_AVREG, 0x0a, 0x50 },
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+ { REQ_07_SET_GET_AVREG, 0x0c, 0x6a },
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+ { REQ_07_SET_GET_AVREG, 0x11, 0xc9 },
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+ { REQ_07_SET_GET_AVREG, 0x12, 0x07 },
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+ { REQ_07_SET_GET_AVREG, 0x13, 0x3b },
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+ { REQ_07_SET_GET_AVREG, 0x14, 0x47 },
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+ { REQ_07_SET_GET_AVREG, 0x15, 0x6f },
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+ { REQ_07_SET_GET_AVREG, 0x17, 0xcd },
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+ { REQ_07_SET_GET_AVREG, 0x18, 0x1e },
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+ { REQ_07_SET_GET_AVREG, 0x19, 0x8b },
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+ { REQ_07_SET_GET_AVREG, 0x1a, 0xa2 },
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+ { REQ_07_SET_GET_AVREG, 0x1b, 0xe9 },
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+ { REQ_07_SET_GET_AVREG, 0x1c, 0x1c },
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+ { REQ_07_SET_GET_AVREG, 0x1d, 0xcc },
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+ { REQ_07_SET_GET_AVREG, 0x1e, 0xcc },
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+ { REQ_07_SET_GET_AVREG, 0x1f, 0xcd },
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+ { REQ_07_SET_GET_AVREG, 0x20, 0x3c },
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+ { REQ_07_SET_GET_AVREG, 0x21, 0x3c },
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+ { REQ_07_SET_GET_AVREG, 0x2d, 0x48 },
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+ { REQ_07_SET_GET_AVREG, 0x2e, 0x88 },
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+ { REQ_07_SET_GET_AVREG, 0x30, 0x22 },
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+ { REQ_07_SET_GET_AVREG, 0x31, 0x61 },
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+ { REQ_07_SET_GET_AVREG, 0x32, 0x74 },
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+ { REQ_07_SET_GET_AVREG, 0x33, 0x1c },
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+ { REQ_07_SET_GET_AVREG, 0x34, 0x74 },
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+ { REQ_07_SET_GET_AVREG, 0x35, 0x1c },
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+ { REQ_07_SET_GET_AVREG, 0x36, 0x7a },
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+ { REQ_07_SET_GET_AVREG, 0x37, 0x26 },
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+ { REQ_07_SET_GET_AVREG, 0x38, 0x40 },
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+ { REQ_07_SET_GET_AVREG, 0x39, 0x0a },
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+ { REQ_07_SET_GET_AVREG, 0x42, 0x55 },
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+ { REQ_07_SET_GET_AVREG, 0x51, 0x11 },
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+ { REQ_07_SET_GET_AVREG, 0x55, 0x01 },
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+ { REQ_07_SET_GET_AVREG, 0x57, 0x02 },
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+ { REQ_07_SET_GET_AVREG, 0x58, 0x35 },
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+ { REQ_07_SET_GET_AVREG, 0x59, 0xa0 },
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+ { REQ_07_SET_GET_AVREG, 0x80, 0x15 },
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+ { REQ_07_SET_GET_AVREG, 0x82, 0x42 },
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+ { REQ_07_SET_GET_AVREG, 0xc1, 0xd0 },
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+ { REQ_07_SET_GET_AVREG, 0xc3, 0x88 },
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+ { REQ_07_SET_GET_AVREG, 0x3f, 0x00 }, /* End of the soft reset */
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+ { REQ_05_SET_GET_USBREG, 0x18, 0x00 },
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+};
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+
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+struct reg_init tm6010_init_tab[] = {
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+ { REQ_07_SET_GET_AVREG, 0xc0, 0x00 },
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+ { REQ_07_SET_GET_AVREG, 0xc4, 0xa0 },
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+ { REQ_07_SET_GET_AVREG, 0xc6, 0x40 },
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+ { REQ_07_SET_GET_AVREG, 0xca, 0x31 },
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+ { REQ_07_SET_GET_AVREG, 0xcc, 0xe1 },
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+ { REQ_07_SET_GET_AVREG, 0xe0, 0x03 },
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+ { REQ_07_SET_GET_AVREG, 0xfe, 0x7f },
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+
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+ { REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0 },
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+ { REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4 },
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+ { REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8 },
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+ { REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00 },
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+ { REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2 },
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+ { REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0 },
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+ { REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2 },
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+ { REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60 },
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+ { REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc },
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+
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+ { REQ_07_SET_GET_AVREG, 0x3f, 0x01 },
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+ { REQ_07_SET_GET_AVREG, 0x00, 0x00 },
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+ { REQ_07_SET_GET_AVREG, 0x01, 0x07 },
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+ { REQ_07_SET_GET_AVREG, 0x02, 0x5f },
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+ { REQ_07_SET_GET_AVREG, 0x03, 0x00 },
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+ { REQ_07_SET_GET_AVREG, 0x05, 0x64 },
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+ { REQ_07_SET_GET_AVREG, 0x07, 0x01 },
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+ { REQ_07_SET_GET_AVREG, 0x08, 0x82 },
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+ { REQ_07_SET_GET_AVREG, 0x09, 0x36 },
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+ { REQ_07_SET_GET_AVREG, 0x0a, 0x50 },
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+ { REQ_07_SET_GET_AVREG, 0x0c, 0x6a },
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+ { REQ_07_SET_GET_AVREG, 0x11, 0xc9 },
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+ { REQ_07_SET_GET_AVREG, 0x12, 0x07 },
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|
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+ { REQ_07_SET_GET_AVREG, 0x13, 0x3b },
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|
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+ { REQ_07_SET_GET_AVREG, 0x14, 0x47 },
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+ { REQ_07_SET_GET_AVREG, 0x15, 0x6f },
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|
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+ { REQ_07_SET_GET_AVREG, 0x17, 0xcd },
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|
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+ { REQ_07_SET_GET_AVREG, 0x18, 0x1e },
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|
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+ { REQ_07_SET_GET_AVREG, 0x19, 0x8b },
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|
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+ { REQ_07_SET_GET_AVREG, 0x1a, 0xa2 },
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|
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+ { REQ_07_SET_GET_AVREG, 0x1b, 0xe9 },
|
|
|
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+ { REQ_07_SET_GET_AVREG, 0x1c, 0x1c },
|
|
|
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+ { REQ_07_SET_GET_AVREG, 0x1d, 0xcc },
|
|
|
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+ { REQ_07_SET_GET_AVREG, 0x1e, 0xcc },
|
|
|
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+ { REQ_07_SET_GET_AVREG, 0x1f, 0xcd },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0x20, 0x3c },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0x21, 0x3c },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0x2d, 0x48 },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0x2e, 0x88 },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0x30, 0x22 },
|
|
|
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+ { REQ_07_SET_GET_AVREG, 0x31, 0x61 },
|
|
|
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+ { REQ_07_SET_GET_AVREG, 0x32, 0x74 },
|
|
|
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+ { REQ_07_SET_GET_AVREG, 0x33, 0x1c },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0x34, 0x74 },
|
|
|
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+ { REQ_07_SET_GET_AVREG, 0x35, 0x1c },
|
|
|
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+ { REQ_07_SET_GET_AVREG, 0x36, 0x7a },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0x37, 0x26 },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0x38, 0x40 },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0x39, 0x0a },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0x42, 0x55 },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0x51, 0x11 },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0x55, 0x01 },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0x57, 0x02 },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0x58, 0x35 },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0x59, 0xa0 },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0x80, 0x15 },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0x82, 0x42 },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0xc1, 0xd0 },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0xc3, 0x88 },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0x3f, 0x00 },
|
|
|
|
+
|
|
|
|
+ { REQ_05_SET_GET_USBREG, 0x18, 0x00 },
|
|
|
|
+
|
|
|
|
+ /* set remote wakeup key:any key wakeup */
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0xe5, 0xfe },
|
|
|
|
+ { REQ_07_SET_GET_AVREG, 0xda, 0xff },
|
|
};
|
|
};
|
|
|
|
|
|
int tm6000_init (struct tm6000_core *dev)
|
|
int tm6000_init (struct tm6000_core *dev)
|
|
{
|
|
{
|
|
- int board, rc=0, i;
|
|
|
|
|
|
+ int board, rc=0, i, size;
|
|
|
|
+ struct reg_init *tab;
|
|
|
|
+
|
|
|
|
+ if (dev->dev_type == TM6010) {
|
|
|
|
+ tab = tm6010_init_tab;
|
|
|
|
+ size = ARRAY_SIZE(tm6010_init_tab);
|
|
|
|
+ } else {
|
|
|
|
+ tab = tm6000_init_tab;
|
|
|
|
+ size = ARRAY_SIZE(tm6000_init_tab);
|
|
|
|
+ }
|
|
|
|
|
|
/* Load board's initialization table */
|
|
/* Load board's initialization table */
|
|
- for (i=0; i< ARRAY_SIZE(init_tab); i++) {
|
|
|
|
- rc= tm6000_set_reg (dev, REQ_07_SET_GET_AVREG,
|
|
|
|
- init_tab[i][0],init_tab[i][1]);
|
|
|
|
|
|
+ for (i=0; i< size; i++) {
|
|
|
|
+ rc= tm6000_set_reg (dev, tab[i].req, tab[i].reg, tab[i].val);
|
|
if (rc<0) {
|
|
if (rc<0) {
|
|
- printk (KERN_ERR "Error %i while setting reg %d to value %d\n",
|
|
|
|
- rc, init_tab[i][0],init_tab[i][1]);
|
|
|
|
|
|
+ printk (KERN_ERR "Error %i while setting req %d, "
|
|
|
|
+ "reg %d to value %d\n", rc,
|
|
|
|
+ tab[i].req,tab[i].reg, tab[i].val);
|
|
return rc;
|
|
return rc;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
|
|
+ msleep(5); /* Just to be conservative */
|
|
|
|
+
|
|
/* Check board version - maybe 10Moons specific */
|
|
/* Check board version - maybe 10Moons specific */
|
|
board=tm6000_get_reg16 (dev, 0x40, 0, 0);
|
|
board=tm6000_get_reg16 (dev, 0x40, 0, 0);
|
|
if (board >=0) {
|
|
if (board >=0) {
|
|
@@ -328,19 +430,24 @@ int tm6000_init (struct tm6000_core *dev)
|
|
printk (KERN_ERR "Error %i while retrieving board version\n",board);
|
|
printk (KERN_ERR "Error %i while retrieving board version\n",board);
|
|
}
|
|
}
|
|
|
|
|
|
- tm6000_set_reg (dev, REQ_05_SET_GET_USBREG, 0x18, 0x00);
|
|
|
|
- msleep(5); /* Just to be conservative */
|
|
|
|
|
|
+ if (dev->dev_type == TM6010) {
|
|
|
|
+ /* Turn xceive 3028 on */
|
|
|
|
+ tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6010_GPIO_3, 0x01);
|
|
|
|
+ msleep(11);
|
|
|
|
+ }
|
|
|
|
|
|
/* Reset GPIO1 and GPIO4. */
|
|
/* Reset GPIO1 and GPIO4. */
|
|
for (i=0; i< 2; i++) {
|
|
for (i=0; i< 2; i++) {
|
|
- rc=tm6000_set_reg (dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_1, 0);
|
|
|
|
|
|
+ rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
|
|
|
|
+ dev->tuner_reset_gpio, 0x00);
|
|
if (rc<0) {
|
|
if (rc<0) {
|
|
printk (KERN_ERR "Error %i doing GPIO1 reset\n",rc);
|
|
printk (KERN_ERR "Error %i doing GPIO1 reset\n",rc);
|
|
return rc;
|
|
return rc;
|
|
}
|
|
}
|
|
|
|
|
|
msleep(10); /* Just to be conservative */
|
|
msleep(10); /* Just to be conservative */
|
|
- rc=tm6000_set_reg (dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_1, 1);
|
|
|
|
|
|
+ rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
|
|
|
|
+ dev->tuner_reset_gpio, 0x01);
|
|
if (rc<0) {
|
|
if (rc<0) {
|
|
printk (KERN_ERR "Error %i doing GPIO1 reset\n",rc);
|
|
printk (KERN_ERR "Error %i doing GPIO1 reset\n",rc);
|
|
return rc;
|
|
return rc;
|
|
@@ -360,8 +467,12 @@ int tm6000_init (struct tm6000_core *dev)
|
|
return rc;
|
|
return rc;
|
|
}
|
|
}
|
|
|
|
|
|
- if (!i)
|
|
|
|
|
|
+ if (!i) {
|
|
rc=tm6000_get_reg16(dev, 0x40,0,0);
|
|
rc=tm6000_get_reg16(dev, 0x40,0,0);
|
|
|
|
+ if (rc>=0) {
|
|
|
|
+ printk ("board=%d\n", rc);
|
|
|
|
+ }
|
|
|
|
+ }
|
|
}
|
|
}
|
|
|
|
|
|
msleep(50);
|
|
msleep(50);
|